soc/intel/tigerlake: Update chip files
Update chip files to include : - Update chip.c based on TGL FSP - Update chip.h based on TGL FSP - Update Kconfig : Define CONFIG_MAX_PCIE_CLOCKS for chip.h update - Update pmc_utils.c and JSL devicetree for build failure Reference PCH EDS#576591 vol1 rev1.2 BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37783 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Ravi Sarawadi
Patrick Georgi
parent
92bd83979f
commit
2fd49721b1
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@ -8,9 +8,9 @@ chip soc/intel/tigerlake
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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# offset bits also need to be changed.
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register "gpe0_dw0" = "GPP_B"
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register "gpe0_dw1" = "GPP_D"
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register "gpe0_dw2" = "GPP_E"
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register "pmc_gpe0_dw0" = "GPP_B"
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register "pmc_gpe0_dw1" = "GPP_D"
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register "pmc_gpe0_dw2" = "GPP_E"
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# FSP configuration
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register "SaGv" = "SaGv_Enabled"
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@ -115,6 +115,11 @@ config MAX_ROOT_PORTS
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default 16 if SOC_INTEL_JASPERLAKE
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default 12 if SOC_INTEL_TIGERLAKE
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config MAX_PCIE_CLOCKS
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int
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default 7 if SOC_INTEL_TIGERLAKE
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default 16 if SOC_INTEL_JASPERLAKE
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config SMM_TSEG_SIZE
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hex
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default 0x800000
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@ -34,29 +34,51 @@ const char *soc_acpi_name(const struct device *dev)
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if (dev->path.type == DEVICE_PATH_DOMAIN)
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return "PCI0";
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if (dev->path.type == DEVICE_PATH_USB) {
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switch (dev->path.usb.port_type) {
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case 0:
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/* Root Hub */
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return "RHUB";
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case 2:
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/* USB2 ports */
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switch (dev->path.usb.port_id) {
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case 0: return "HS01";
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case 1: return "HS02";
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case 2: return "HS03";
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case 3: return "HS04";
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case 4: return "HS05";
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case 5: return "HS06";
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case 6: return "HS07";
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case 7: return "HS08";
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case 8: return "HS09";
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case 9: return "HS10";
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}
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break;
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case 3:
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/* USB3 ports */
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switch (dev->path.usb.port_id) {
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case 0: return "SS01";
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case 1: return "SS02";
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case 2: return "SS03";
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case 3: return "SS04";
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}
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break;
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}
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return NULL;
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}
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if (dev->path.type != DEVICE_PATH_PCI)
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return NULL;
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switch (dev->path.pci.devfn) {
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case SA_DEVFN_ROOT: return "MCHC";
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case SA_DEVFN_IGD: return "GFX0";
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case PCH_DEVFN_ISH: return "ISHB";
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case PCH_DEVFN_XHCI: return "XHCI";
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case PCH_DEVFN_USBOTG: return "XDCI";
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case PCH_DEVFN_THERMAL: return "THRM";
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case PCH_DEVFN_I2C0: return "I2C0";
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case PCH_DEVFN_I2C1: return "I2C1";
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case PCH_DEVFN_I2C2: return "I2C2";
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case PCH_DEVFN_I2C3: return "I2C3";
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case PCH_DEVFN_CSE: return "CSE1";
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case PCH_DEVFN_CSE_2: return "CSE2";
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case PCH_DEVFN_CSE_IDER: return "CSED";
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case PCH_DEVFN_CSE_KT: return "CSKT";
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case PCH_DEVFN_CSE_3: return "CSE3";
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case PCH_DEVFN_SATA: return "SATA";
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case PCH_DEVFN_UART2: return "UAR2";
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case PCH_DEVFN_I2C4: return "I2C4";
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case PCH_DEVFN_I2C5: return "I2C5";
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case PCH_DEVFN_SATA: return "SATA";
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case PCH_DEVFN_PCIE1: return "RP01";
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case PCH_DEVFN_PCIE2: return "RP02";
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case PCH_DEVFN_PCIE3: return "RP03";
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@ -69,34 +91,17 @@ const char *soc_acpi_name(const struct device *dev)
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case PCH_DEVFN_PCIE10: return "RP10";
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case PCH_DEVFN_PCIE11: return "RP11";
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case PCH_DEVFN_PCIE12: return "RP12";
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case PCH_DEVFN_PCIE13: return "RP13";
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case PCH_DEVFN_PCIE14: return "RP14";
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case PCH_DEVFN_PCIE15: return "RP15";
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case PCH_DEVFN_PCIE16: return "RP16";
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case PCH_DEVFN_PCIE17: return "RP17";
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case PCH_DEVFN_PCIE18: return "RP18";
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case PCH_DEVFN_PCIE19: return "RP19";
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case PCH_DEVFN_PCIE20: return "RP20";
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case PCH_DEVFN_PCIE21: return "RP21";
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case PCH_DEVFN_PCIE22: return "RP22";
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case PCH_DEVFN_PCIE23: return "RP23";
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case PCH_DEVFN_PCIE24: return "RP24";
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case PCH_DEVFN_UART0: return "UAR0";
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case PCH_DEVFN_UART1: return "UAR1";
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case PCH_DEVFN_UART2: return "UAR2";
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case PCH_DEVFN_GSPI0: return "SPI0";
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case PCH_DEVFN_GSPI1: return "SPI1";
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case PCH_DEVFN_GSPI2: return "SPI2";
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case PCH_DEVFN_EMMC: return "EMMC";
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case PCH_DEVFN_SDCARD: return "SDXC";
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/* Keeping ACPI device name coherent with ec.asl */
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case PCH_DEVFN_ESPI: return "LPCB";
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case PCH_DEVFN_P2SB: return "P2SB";
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case PCH_DEVFN_PMC: return "PMC_";
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case PCH_DEVFN_HDA: return "HDAS";
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case PCH_DEVFN_SMBUS: return "SBUS";
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case PCH_DEVFN_SPI: return "FSPI";
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case PCH_DEVFN_GBE: return "IGBE";
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case PCH_DEVFN_TRACEHUB:return "THUB";
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case PCH_DEVFN_GBE: return "GLAN";
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}
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return NULL;
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@ -146,9 +151,9 @@ static struct device_operations pci_domain_ops = {
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.read_resources = &pci_domain_read_resources,
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.set_resources = &pci_domain_set_resources,
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.scan_bus = &pci_domain_scan_bus,
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#if CONFIG(HAVE_ACPI_TABLES)
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#if CONFIG(HAVE_ACPI_TABLES)
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.acpi_name = &soc_acpi_name,
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#endif
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#endif
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};
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static struct device_operations cpu_bus_ops = {
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@ -36,10 +36,10 @@ struct soc_intel_tigerlake_config {
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struct soc_intel_common_config common_soc_config;
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/* Gpio group routed to each dword of the GPE0 block. Values are
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* of the form GPP_[A:G] or GPD. */
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uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */
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uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */
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uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */
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* of the form PMC_GPP_[A:U] or GPD. */
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uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */
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uint8_t pmc_gpe0_dw1; /* GPE0_63_32 STS/EN */
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uint8_t pmc_gpe0_dw2; /* GPE0_95_64 STS/EN */
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/* Generic IO decode ranges */
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uint32_t gen1_dec;
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@ -67,43 +67,25 @@ struct soc_intel_tigerlake_config {
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/* TCC activation offset */
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uint32_t tcc_offset;
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uint64_t PlatformMemorySize;
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uint8_t SmramMask;
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uint8_t MrcFastBoot;
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uint32_t TsegSize;
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uint16_t MmioSize;
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/* DDR Frequency Limit. Maximum Memory Frequency Selections in Mhz.
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* Options : 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933, 0(Auto) */
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uint16_t DdrFreqLimit;
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/* SAGV Low Frequency Selections in Mhz.
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* Options : 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933, 0(Auto) */
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uint16_t FreqSaGvLow;
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/* SAGV Mid Frequency Selections in Mhz.
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* Options : 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933, 0(Auto) */
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uint16_t FreqSaGvMid;
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/* System Agent dynamic frequency support. Only effects ULX/ULT CPUs.
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* When enabled memory will be training at two different frequencies.
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* 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled */
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* 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2,
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* 4:FixedPoint3, 5:Enabled */
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enum {
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SaGv_Disabled,
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SaGv_FixedLow,
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SaGv_FixedMid,
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SaGv_FixedHigh,
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SaGv_FixedPoint0,
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SaGv_FixedPoint1,
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SaGv_FixedPoint2,
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SaGv_FixedPoint3,
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SaGv_Enabled,
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} SaGv;
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/* Rank Margin Tool. 1:Enable, 0:Disable */
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uint8_t RMT;
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/* USB related */
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struct usb2_port_config usb2_ports[16];
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struct usb3_port_config usb3_ports[10];
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uint8_t SsicPortEnable;
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/* Wake Enable Bitmap for USB2 ports */
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uint16_t usb2_wake_enable_bitmap;
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/* Wake Enable Bitmap for USB3 ports */
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@ -137,24 +119,16 @@ struct soc_intel_tigerlake_config {
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/* PCIe output clocks type to Pcie devices.
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* 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
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* 0xFF: not used */
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uint8_t PcieClkSrcUsage[CONFIG_MAX_ROOT_PORTS];
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uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS];
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/* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to
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* clksrc. */
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uint8_t PcieClkSrcClkReq[CONFIG_MAX_ROOT_PORTS];
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uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS];
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/* SMBus */
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uint8_t SmbusEnable;
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/* eMMC and SD */
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uint8_t ScsEmmcHs400Enabled;
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/* Need to update DLL setting to get Emmc running at HS400 speed */
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uint8_t EmmcUseCustomDlls;
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uint32_t EmmcTxCmdDelayRegValue;
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uint32_t EmmcTxDataDelay1RegValue;
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uint32_t EmmcTxDataDelay2RegValue;
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uint32_t EmmcRxCmdDataDelay1RegValue;
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uint32_t EmmcRxCmdDataDelay2RegValue;
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uint32_t EmmcRxStrobeDelayRegValue;
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/* Enable if SD Card Power Enable Signal is Active High */
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uint8_t SdCardPowerEnableActiveHigh;
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@ -173,14 +147,6 @@ struct soc_intel_tigerlake_config {
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uint32_t GraphicsConfigPtr;
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uint8_t Device4Enable;
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/* GPIO IRQ Select. The valid value is 14 or 15 */
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uint8_t GpioIrqRoute;
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/* SCI IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23 */
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uint8_t SciIrqSelect;
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/* TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23 */
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uint8_t TcoIrqSelect;
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uint8_t TcoIrqEnable;
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/* HeciEnabled decides the state of Heci1 at end of boot
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* Setting to 0 (default) disables Heci1 and hides the device from OS */
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uint8_t HeciEnabled;
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@ -188,21 +154,23 @@ struct soc_intel_tigerlake_config {
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uint32_t tdp_pl2_override;
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/* Intel Speed Shift Technology */
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uint8_t speed_shift_enable;
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/* Enable VR specific mailbox command
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* 00b - no VR specific cmd sent
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* 01b - VR mailbox cmd specifically for the MPS IMPV8 VR will be sent
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* 10b - VR specific cmd sent for PS4 exit issue
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* 11b - Reserved */
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uint8_t SendVrMbxCmd;
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/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
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uint8_t eist_enable;
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/* Enable C6 DRAM */
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uint8_t enable_c6dram;
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/*
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* PRMRR size setting with below options
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* Disable: 0x0
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* 32MB: 0x2000000
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* 64MB: 0x4000000
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* 128 MB: 0x8000000
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* 256 MB: 0x10000000
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* 512 MB: 0x20000000
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*/
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uint32_t PrmrrSize;
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uint8_t PmTimerDisabled;
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/* Desired platform debug type. */
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enum {
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DebugConsent_Disabled,
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@ -211,6 +179,8 @@ struct soc_intel_tigerlake_config {
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DebugConsent_USB3_DBC,
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DebugConsent_XDP, /* XDP/Mipi60 */
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DebugConsent_USB2_DBC,
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DebugConsent_2WIRE_DCI,
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DebugConsent_Manual,
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} DebugConsent;
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/*
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* SerialIO device mode selection:
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@ -244,9 +214,8 @@ struct soc_intel_tigerlake_config {
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/* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */
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enum {
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PLATFORM_POR,
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FORCE_ENABLE,
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FORCE_DISABLE,
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FORCE_ENABLE,
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} CnviBtAudioOffload;
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/*
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@ -189,9 +189,9 @@ void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
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config = config_of_soc();
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/* Assign to out variable */
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*dw0 = config->gpe0_dw0;
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*dw1 = config->gpe0_dw1;
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*dw2 = config->gpe0_dw2;
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*dw0 = config->pmc_gpe0_dw0;
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*dw1 = config->pmc_gpe0_dw1;
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*dw2 = config->pmc_gpe0_dw2;
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}
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static int rtc_failed(uint32_t gen_pmcon_b)
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