soc/intel/apl: Implement power-failure-state API
Needed some Makefile changes to be able to compile for SMM. Change-Id: Ibf218b90088a45349c54f4b881e895bb852e88bb Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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4 changed files with 23 additions and 1 deletions
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@ -39,6 +39,7 @@ romstage-y += reset.c
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romstage-y += spi.c
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romstage-y += spi.c
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smm-y += mmap_boot.c
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smm-y += mmap_boot.c
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smm-y += pmc.c
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smm-y += pmutil.c
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smm-y += pmutil.c
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smm-y += smihandler.c
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smm-y += smihandler.c
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smm-y += spi.c
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smm-y += spi.c
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@ -172,6 +172,7 @@
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#define SRS (1 << 20)
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#define SRS (1 << 20)
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#define MS4V (1 << 18)
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#define MS4V (1 << 18)
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#define RPS (1 << 2)
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#define RPS (1 << 2)
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#define SLEEP_AFTER_POWER_FAIL (1 << 0)
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#define GEN_PMCON1_CLR1_BITS (COLD_BOOT_STS | COLD_RESET_STS | \
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#define GEN_PMCON1_CLR1_BITS (COLD_BOOT_STS | COLD_RESET_STS | \
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WARM_RESET_STS | GLOBAL_RESET_STS | \
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WARM_RESET_STS | GLOBAL_RESET_STS | \
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SRS | MS4V)
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SRS | MS4V)
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@ -92,6 +92,24 @@ static void set_slp_s3_assertion_width(int width_usecs)
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write32((void *)gen_pmcon3, reg);
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write32((void *)gen_pmcon3, reg);
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}
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}
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void pmc_soc_set_afterg3_en(const bool on)
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{
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void *const gen_pmcon1 = (void *)(soc_read_pmc_base() + GEN_PMCON1);
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uint32_t reg32;
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reg32 = read32(gen_pmcon1);
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if (on)
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reg32 &= ~SLEEP_AFTER_POWER_FAIL;
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else
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reg32 |= SLEEP_AFTER_POWER_FAIL;
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write32(gen_pmcon1, reg32);
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}
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void pmc_soc_restore_power_failure(void)
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{
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pmc_set_power_failure_state(false);
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}
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void pmc_soc_init(struct device *dev)
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void pmc_soc_init(struct device *dev)
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{
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{
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const struct soc_intel_apollolake_config *cfg = config_of(dev);
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const struct soc_intel_apollolake_config *cfg = config_of(dev);
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@ -108,4 +126,6 @@ void pmc_soc_init(struct device *dev)
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/* Now that things have been logged clear out the PMC state. */
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/* Now that things have been logged clear out the PMC state. */
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pmc_clear_prsts();
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pmc_clear_prsts();
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pmc_set_power_failure_state(true);
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}
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}
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@ -13,8 +13,8 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI) += fast_spi_flash.c
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postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI) += fast_spi.c
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postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI) += fast_spi.c
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postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI) += fast_spi_flash.c
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postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI) += fast_spi_flash.c
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ifeq ($(CONFIG_SPI_FLASH_SMM),y)
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smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI) += fast_spi.c
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smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI) += fast_spi.c
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ifeq ($(CONFIG_SPI_FLASH_SMM),y)
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smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI) += fast_spi_flash.c
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smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI) += fast_spi_flash.c
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endif
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endif
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