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soc/amd/common: Add PM_ESPI_INTR_CTRL 

This register is used for masking/unmasking eSPI IRQs.

BUG=none
TEST=Build guybrush

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia209539b2e0ce390e227757b16c2969b9124a845
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52142
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Raul E Rangel 2021-04-06 15:41:22 -06:00 committed by Patrick Georgi
parent 3db49929bd
commit 2ff76be15c
1 changed files with 2 additions and 0 deletions
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2
src/soc/amd/common/block/include/amdblocks/acpimmio.h
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@ -26,6 +26,8 @@
#define LEGACY_DMA_IO_EN (1 << 2) #define LEGACY_DMA_IO_EN (1 << 2)
#define CF9_IO_EN (1 << 1) #define CF9_IO_EN (1 << 1)
#define LEGACY_IO_EN (1 << 0) #define LEGACY_IO_EN (1 << 0)
#define PM_ESPI_INTR_CTRL 0x40
#define PM_ESPI_DEV_INTR_MASK 0x00FFFFFF
#define PM_RST_CTRL1 0xbe #define PM_RST_CTRL1 0xbe
#define SLPTYPE_CONTROL_EN (1 << 5) #define SLPTYPE_CONTROL_EN (1 << 5)
#define KBRSTEN (1 << 4) #define KBRSTEN (1 << 4)