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soc/intel/tigerlake: Add TGL-H power limits 

Convert the power limit defines to an enum and add TGL-H entries.

Change-Id: I6fa7c7338b3157b29ff72769238597e3c528aedb
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Jeremy Soller 2021-08-12 10:49:58 -06:00 committed by Felix Held
parent 49759f6025
commit 301b09b3e6
2 changed files with 15 additions and 5 deletions
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14
src/soc/intel/tigerlake/chip.h
View File

@ -24,11 +24,15 @@
#define MAX_HD_AUDIO_SSP_LINKS 6
/* The first two are for TGL-U */
#define POWER_LIMITS_U_2_CORE 0
#define POWER_LIMITS_U_4_CORE 1
#define POWER_LIMITS_Y_2_CORE 2
#define POWER_LIMITS_Y_4_CORE 3
#define POWER_LIMITS_MAX 4
enum soc_intel_tigerlake_power_limits {
POWER_LIMITS_U_2_CORE,
POWER_LIMITS_U_4_CORE,
POWER_LIMITS_Y_2_CORE,
POWER_LIMITS_Y_4_CORE,
POWER_LIMITS_H_6_CORE,
POWER_LIMITS_H_8_CORE,
POWER_LIMITS_MAX
};
/*
* Enable External V1P05 Rail in: BIT0:S0i1/S0i2,

6
src/soc/intel/tigerlake/systemagent.c
View File

@ -90,6 +90,12 @@ void soc_systemagent_init(struct device *dev)
case PCI_DEVICE_ID_INTEL_TGL_ID_Y_4_2:
soc_config = &config->power_limits_config[POWER_LIMITS_Y_4_CORE];
break;
case PCI_DEVICE_ID_INTEL_TGL_ID_H_6_1:
soc_config = &config->power_limits_config[POWER_LIMITS_H_6_CORE];
break;
case PCI_DEVICE_ID_INTEL_TGL_ID_H_8_1:
soc_config = &config->power_limits_config[POWER_LIMITS_H_8_CORE];
break;
default:
printk(BIOS_ERR, "TGL: unknown SA ID: 0x%4x, skipping power limits "
"configuration\n", sa_pci_id);