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soc/intel/apollolake: Removing some menuconfig options 

Does not need to changeable in menuconfig.

Change-Id: Id488f7333952d10d10a62ac75298ec8008e6f9b4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This commit is contained in:
Arthur Heymans 2017-06-13 14:05:09 +02:00 committed by Martin Roth
parent 95d6dd21c9
commit 3038b48de3
1 changed files with 3 additions and 3 deletions
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6
src/soc/intel/apollolake/Kconfig
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@ -113,11 +113,11 @@ config PCR_BASE_ADDRESS
This option allows you to select MMIO Base Address of sideband bus. This option allows you to select MMIO Base Address of sideband bus.
config DCACHE_RAM_BASE config DCACHE_RAM_BASE
hex "Base address of cache-as-RAM" hex
default 0xfef00000 default 0xfef00000
config DCACHE_RAM_SIZE config DCACHE_RAM_SIZE
hex "Length in bytes of cache-as-RAM" hex
default 0xc0000 default 0xc0000
help help
The size of the cache-as-ram region required during bootblock The size of the cache-as-ram region required during bootblock
@ -140,7 +140,7 @@ config SOC_INTEL_COMMON_LPSS_CLOCK_MHZ
config CONSOLE_UART_BASE_ADDRESS config CONSOLE_UART_BASE_ADDRESS
depends on CONSOLE_SERIAL depends on CONSOLE_SERIAL
hex "MMIO base address for UART" hex
default 0xde000000 default 0xde000000
config SOC_UART_DEBUG config SOC_UART_DEBUG