soc/intel/apollolake: Removing some menuconfig options
Does not need to changeable in menuconfig. Change-Id: Id488f7333952d10d10a62ac75298ec8008e6f9b4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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@ -113,11 +113,11 @@ config PCR_BASE_ADDRESS
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This option allows you to select MMIO Base Address of sideband bus.
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config DCACHE_RAM_BASE
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hex "Base address of cache-as-RAM"
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hex
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default 0xfef00000
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config DCACHE_RAM_SIZE
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hex "Length in bytes of cache-as-RAM"
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hex
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default 0xc0000
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help
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The size of the cache-as-ram region required during bootblock
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@ -140,7 +140,7 @@ config SOC_INTEL_COMMON_LPSS_CLOCK_MHZ
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config CONSOLE_UART_BASE_ADDRESS
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depends on CONSOLE_SERIAL
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hex "MMIO base address for UART"
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hex
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default 0xde000000
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config SOC_UART_DEBUG
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