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hatch: Create puff variant 

Includes:
 - gpio mappings,
 - overridetree.cb,
 - kconfig adjustments for reading spd over smbus.

V.2: Rework devicetree with comments and drop some useless gpio maps.

BUG=b:141658115
TEST=./util/abuild/abuild -p none -t google/hatch -x -a

Change-Id: I6449c4fcc1df702ed4f0d35afd7b0981e4c72323
Signed-off-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Edward O'Callaghan 2019-10-30 16:18:25 +11:00 committed by Furquan Shaikh
parent 881f9cb715
commit 3042af6256
8 changed files with 223 additions and 0 deletions
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2
src/mainboard/google/hatch/Kconfig
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@ -93,6 +93,7 @@ config MAINBOARD_PART_NUMBER
default "Helios" if BOARD_GOOGLE_HELIOS
default "Kindred" if BOARD_GOOGLE_KINDRED
default "Kohaku" if BOARD_GOOGLE_KOHAKU
default "Puff" if BOARD_GOOGLE_PUFF
config MAINBOARD_VENDOR
string
@ -118,6 +119,7 @@ config VARIANT_DIR
default "helios" if BOARD_GOOGLE_HELIOS
default "kindred" if BOARD_GOOGLE_KINDRED
default "kohaku" if BOARD_GOOGLE_KOHAKU
default "puff" if BOARD_GOOGLE_PUFF
config VBOOT
select HAS_RECOVERY_MRC_CACHE

6
src/mainboard/google/hatch/Kconfig.name
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@ -32,3 +32,9 @@ config BOARD_GOOGLE_HELIOS
select BOARD_ROMSIZE_KB_16384
select CHROMEOS_DSM_CALIB
select DRIVERS_I2C_RT1011
config BOARD_GOOGLE_PUFF
bool "-> Puff"
select BOARD_GOOGLE_BASEBOARD_HATCH
select BOARD_ROMSIZE_KB_32768
select ROMSTAGE_SPD_SMBUS

16
src/mainboard/google/hatch/variants/puff/Makefile.inc Normal file
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@ -0,0 +1,16 @@
## This file is part of the coreboot project.
##
## Copyright 2019 Google LLC
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
ramstage-y += gpio.c
bootblock-y += gpio.c

56
src/mainboard/google/hatch/variants/puff/gpio.c Normal file
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@ -0,0 +1,56 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2019 Google LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
* GNU General Public License for more details.
*/
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <commonlib/helpers.h>
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
/* B14 : GPP_B14_STRAP */
PAD_NC(GPP_B14, NONE),
/* B22 : GPP_B22_STRAP */
PAD_NC(GPP_B22, NONE),
/* E19 : GPP_E19_STRAP */
PAD_NC(GPP_E19, NONE),
/* E21 : GPP_E21_STRAP */
PAD_NC(GPP_E21, NONE),
/* B15 : H1_SLAVE_SPI_CS_L */
PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
/* B16 : H1_SLAVE_SPI_CLK */
PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
/* B17 : H1_SLAVE_SPI_MISO_R */
PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
/* B18 : H1_SLAVE_SPI_MOSI_R */
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
/* C14 : BT_DISABLE_L */
PAD_CFG_GPO(GPP_C14, 0, DEEP),
/* PCH_WP_OD */
PAD_CFG_GPI(GPP_C20, NONE, DEEP),
/* C21 : H1_PCH_INT_ODL */
PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
/* C23 : WLAN_PE_RST# */
PAD_CFG_GPO(GPP_C23, 1, DEEP),
/* E1 : M2_SSD_PEDET */
PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
/* E5 : SATA_DEVSLP1 */
PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1),
};
const struct pad_config *variant_early_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(early_gpio_table);
return early_gpio_table;
}

1
src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl Normal file
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@ -0,0 +1 @@
#include <baseboard/acpi/dptf.asl>

21
src/mainboard/google/hatch/variants/puff/include/variant/ec.h Normal file
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@ -0,0 +1,21 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2019 Google LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef VARIANT_EC_H
#define VARIANT_EC_H
#include <baseboard/ec.h>
#endif

21
src/mainboard/google/hatch/variants/puff/include/variant/gpio.h Normal file
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@ -0,0 +1,21 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2019 Google LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
* GNU General Public License for more details.
*/
#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H
#include <baseboard/gpio.h>
#endif

100
src/mainboard/google/hatch/variants/puff/overridetree.cb Normal file
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@ -0,0 +1,100 @@
chip soc/intel/cannonlake
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoDisabled,
[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
[PchSerialIoIndexI2C2] = PchSerialIoPci,
[PchSerialIoIndexI2C3] = PchSerialIoPci,
[PchSerialIoIndexI2C4] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoPci,
[PchSerialIoIndexSPI0] = PchSerialIoPci,
[PchSerialIoIndexSPI1] = PchSerialIoPci,
[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
[PchSerialIoIndexUART2] = PchSerialIoDisabled,
}"
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| GSPI0 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
#| | before memory is up |
#| I2C0 | RFU |
#| I2C2 | PS175 |
#| I2C3 | MST |
#| I2C4 | Audio |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.gspi[0] = {
.speed_mhz = 1,
.early_init = 1,
},
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 0,
.fall_time_ns = 0,
},
.i2c[1] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 0,
.fall_time_ns = 0,
},
.i2c[3] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 0,
.fall_time_ns = 0,
},
.i2c[4] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 0,
.fall_time_ns = 0,
},
}"
# GPIO for SD card detect
register "sdcard_cd_gpio" = "vSD3_CD_B"
device domain 0 on
device pci 15.0 off
# RFU - Reserved for Future Use.
end # I2C #0
device pci 15.1 off end # I2C #1
device pci 15.2 on
# chip drivers/i2c/generic
# register "name" = ""PS175""
# register "desc" = ""PCON PS175""
# register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)"
# register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C11)"
# register "has_power_resource" = "1"
# device i2c 15 on end
# end
end # I2C #2
device pci 15.3 on
# chip drivers/i2c/generic
# register "name" = ""RTD21""
# register "desc" = ""Realtek RTD2142""
# device i2c 4a on end
# end
end # I2C #3
device pci 19.0 on
chip drivers/i2c/generic
register "hid" = ""10EC5682""
register "name" = ""RT58""
register "desc" = ""Realtek RT5682""
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)"
register "property_count" = "1"
# Set the jd_src to RT5668_JD1 for jack detection
register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
register "property_list[0].name" = ""realtek,jd-src""
register "property_list[0].integer" = "1"
device i2c 1a on end
end
end #I2C #4
device pci 1e.3 off end # GSPI #1
end
end