mb/google,samsung/*: Add LPC TPM chip driver to devicetree

With commits 9987534 [southbridge/intel: Remove leftover TPM ACPI code]
and 66ce18c [soc/intel: Remove legacy static TPM asl code] removing
TPM ASL code from the southbridge's LPCB device, the LPC TPM chip driver
(drivers/pc80/tpm) must be added to devicetree in order to ensure the
new acpigen code is used to replace it.

Test: boot various google/samsung boards, verify SSDT created with 
LPBC.TPM device and TPM visible to and usable by SeaBIOS and Linux

Change-Id: Iedaa01f26fb357914549bb3dda24b0bd6ef67480
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27786
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/beltino/devicetree.cb

@@ -96,6 +96,9 @@ chip northbridge/intel/haswell
 			device pci 1d.0 on end # USB2 EHCI
 			device pci 1e.0 off end # PCI bridge
 			device pci 1f.0 on
+				chip drivers/pc80/tpm
+					device pnp 0c31.0 on end
+				end
 				chip superio/ite/it8772f
 					# Skip keyboard init
 					register "skip_keyboard" = "1"

src/mainboard/google/butterfly/devicetree.cb

@@ -87,6 +87,9 @@ chip northbridge/intel/sandybridge
 			device pci 1d.0 on end # USB2 EHCI #1
 			device pci 1e.0 off end # PCI bridge
 			device pci 1f.0 on #LPC bridge
+				chip drivers/pc80/tpm
+					device pnp 0c31.0 on end
+				end
 				chip ec/quanta/ene_kb3940q
 					# 60/64 KBC
 					device pnp ff.1 on # dummy address

src/mainboard/google/jecht/devicetree.cb

@@ -76,6 +76,9 @@ chip soc/intel/broadwell
 		device pci 1d.0 on end # USB2 EHCI
 		device pci 1e.0 off end # PCI bridge
 		device pci 1f.0 on
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
 			chip superio/ite/it8772f
 				# Skip keyboard init
 				register "skip_keyboard" = "1"

src/mainboard/google/link/devicetree.cb

@@ -86,6 +86,9 @@ chip northbridge/intel/sandybridge
 			device pci 1d.0 on end # USB2 EHCI #1
 			device pci 1e.0 off end # PCI bridge
 			device pci 1f.0 on
+				chip drivers/pc80/tpm
+					device pnp 0c31.0 on end
+				end
 				chip ec/google/chromeec
 					# We only have one init function that
 					# we need to call to initialize the

src/mainboard/google/rambi/variants/banjo/devicetree.cb

@@ -88,6 +88,9 @@ chip soc/intel/baytrail
 		device pci 1e.4 off end # HSUART2
 		device pci 1e.5 off end # SPI
 		device pci 1f.0 on
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
 			chip ec/google/chromeec
 				# We only have one init function that
 				# we need to call to initialize the

src/mainboard/google/rambi/variants/candy/devicetree.cb

@@ -89,6 +89,9 @@ chip soc/intel/baytrail
 		device pci 1e.4 off end # HSUART2
 		device pci 1e.5 off end # SPI
 		device pci 1f.0 on
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
 			chip ec/google/chromeec
 				# We only have one init function that
 				# we need to call to initialize the

src/mainboard/google/rambi/variants/clapper/devicetree.cb

@@ -76,6 +76,9 @@ chip soc/intel/baytrail
 		device pci 1e.4 off end # HSUART2
 		device pci 1e.5 off end # SPI
 		device pci 1f.0 on
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
 			chip ec/google/chromeec
 				# We only have one init function that
 				# we need to call to initialize the

src/mainboard/google/rambi/variants/enguarde/devicetree.cb

@@ -88,6 +88,9 @@ chip soc/intel/baytrail
 		device pci 1e.4 off end # HSUART2
 		device pci 1e.5 off end # SPI
 		device pci 1f.0 on
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
 			chip ec/google/chromeec
 				# We only have one init function that
 				# we need to call to initialize the

src/mainboard/google/rambi/variants/glimmer/devicetree.cb

@@ -85,6 +85,9 @@ chip soc/intel/baytrail
 		device pci 1e.4 off end # HSUART2
 		device pci 1e.5 off end # SPI
 		device pci 1f.0 on
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
 			chip ec/google/chromeec
 				# We only have one init function that
 				# we need to call to initialize the

src/mainboard/google/rambi/variants/gnawty/devicetree.cb

@@ -88,6 +88,9 @@ chip soc/intel/baytrail
 		device pci 1e.4 off end # HSUART2
 		device pci 1e.5 off end # SPI
 		device pci 1f.0 on
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
 			chip ec/google/chromeec
 				# We only have one init function that
 				# we need to call to initialize the

src/mainboard/google/rambi/variants/heli/devicetree.cb

@@ -89,6 +89,9 @@ chip soc/intel/baytrail
 		device pci 1e.4 off end # HSUART2
 		device pci 1e.5 off end # SPI
 		device pci 1f.0 on
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
 			chip ec/google/chromeec
 				# We only have one init function that
 				# we need to call to initialize the

src/mainboard/google/rambi/variants/kip/devicetree.cb

@@ -88,6 +88,9 @@ chip soc/intel/baytrail
 		device pci 1e.4 off end # HSUART2
 		device pci 1e.5 off end # SPI
 		device pci 1f.0 on
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
 			chip ec/google/chromeec
 				# We only have one init function that
 				# we need to call to initialize the

src/mainboard/google/rambi/variants/ninja/devicetree.cb

@@ -89,6 +89,9 @@ chip soc/intel/baytrail
 		device pci 1e.4 off end # HSUART2
 		device pci 1e.5 off end # SPI
 		device pci 1f.0 on
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
 			chip ec/google/chromeec
 				# We only have one init function that
 				# we need to call to initialize the

src/mainboard/google/rambi/variants/orco/devicetree.cb

@@ -88,6 +88,9 @@ chip soc/intel/baytrail
 		device pci 1e.4 off end # HSUART2
 		device pci 1e.5 off end # SPI
 		device pci 1f.0 on
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
 			chip ec/google/chromeec
 				# We only have one init function that
 				# we need to call to initialize the

src/mainboard/google/rambi/variants/quawks/devicetree.cb

@@ -85,6 +85,9 @@ chip soc/intel/baytrail
 		device pci 1e.4 off end # HSUART2
 		device pci 1e.5 off end # SPI
 		device pci 1f.0 on
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
 			chip ec/google/chromeec
 				# We only have one init function that
 				# we need to call to initialize the

src/mainboard/google/rambi/variants/rambi/devicetree.cb

@@ -89,6 +89,9 @@ chip soc/intel/baytrail
 		device pci 1e.4 off end # HSUART2
 		device pci 1e.5 off end # SPI
 		device pci 1f.0 on
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
 			chip ec/google/chromeec
 				# We only have one init function that
 				# we need to call to initialize the

src/mainboard/google/rambi/variants/squawks/devicetree.cb

@@ -85,6 +85,9 @@ chip soc/intel/baytrail
 		device pci 1e.4 off end # HSUART2
 		device pci 1e.5 off end # SPI
 		device pci 1f.0 on
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
 			chip ec/google/chromeec
 				# We only have one init function that
 				# we need to call to initialize the

src/mainboard/google/rambi/variants/sumo/devicetree.cb

@@ -89,6 +89,9 @@ chip soc/intel/baytrail
 		device pci 1e.4 off end # HSUART2
 		device pci 1e.5 off end # SPI
 		device pci 1f.0 on
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
 			chip ec/google/chromeec
 				# We only have one init function that
 				# we need to call to initialize the

src/mainboard/google/rambi/variants/swanky/devicetree.cb

@@ -88,6 +88,9 @@ chip soc/intel/baytrail
 		device pci 1e.4 off end # HSUART2
 		device pci 1e.5 off end # SPI
 		device pci 1f.0 on
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
 			chip ec/google/chromeec
 				# We only have one init function that
 				# we need to call to initialize the

src/mainboard/google/rambi/variants/winky/devicetree.cb

@@ -89,6 +89,9 @@ chip soc/intel/baytrail
 		device pci 1e.4 off end # HSUART2
 		device pci 1e.5 off end # SPI
 		device pci 1f.0 on
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
 			chip ec/google/chromeec
 				# We only have one init function that
 				# we need to call to initialize the

src/mainboard/google/slippy/variants/falco/devicetree.cb

@@ -109,6 +109,9 @@ chip northbridge/intel/haswell
 			device pci 1d.0 on end # USB2 EHCI
 			device pci 1e.0 off end # PCI bridge
 			device pci 1f.0 on
+				chip drivers/pc80/tpm
+					device pnp 0c31.0 on end
+				end
 				chip ec/google/chromeec
 					# We only have one init function that
 					# we need to call to initialize the

src/mainboard/google/slippy/variants/leon/devicetree.cb

@@ -114,6 +114,9 @@ chip northbridge/intel/haswell
 			device pci 1d.0 on end # USB2 EHCI
 			device pci 1e.0 off end # PCI bridge
 			device pci 1f.0 on
+				chip drivers/pc80/tpm
+					device pnp 0c31.0 on end
+				end
 				chip ec/google/chromeec
 					# We only have one init function that
 					# we need to call to initialize the

src/mainboard/google/slippy/variants/peppy/devicetree.cb

@@ -113,6 +113,9 @@ chip northbridge/intel/haswell
 			device pci 1d.0 on end # USB2 EHCI
 			device pci 1e.0 off end # PCI bridge
 			device pci 1f.0 on
+				chip drivers/pc80/tpm
+					device pnp 0c31.0 on end
+				end
 				chip ec/google/chromeec
 					# We only have one init function that
 					# we need to call to initialize the

src/mainboard/google/slippy/variants/wolf/devicetree.cb

@@ -114,6 +114,9 @@ chip northbridge/intel/haswell
 			device pci 1d.0 on end # USB2 EHCI
 			device pci 1e.0 off end # PCI bridge
 			device pci 1f.0 on
+				chip drivers/pc80/tpm
+					device pnp 0c31.0 on end
+				end
 				chip ec/google/chromeec
 					# We only have one init function that
 					# we need to call to initialize the

src/mainboard/google/stout/devicetree.cb

@@ -97,6 +97,9 @@ chip northbridge/intel/sandybridge
 			device pci 1d.0 on end # USB2 EHCI #1 (Camera, WLAN, WWAN)
 			device pci 1e.0 off end # PCI bridge
 			device pci 1f.0 on
+				chip drivers/pc80/tpm
+					device pnp 0c31.0 on end
+				end
 				chip ec/quanta/it8518
 					# 60h/64h KBC
 					device pnp ff.1 on # dummy address

src/mainboard/samsung/lumpy/devicetree.cb

@@ -119,6 +119,9 @@ chip northbridge/intel/sandybridge
 				     register "base" = "(void *)0xfec00000"
 				     device ioapic 4 on end
 				end
+				chip drivers/pc80/tpm
+					device pnp 0c31.0 on end
+				end
 			end
 			device pci 1f.2 on # SATA Controller 1
 				ioapic_irq 4 INTA 0x10

src/mainboard/samsung/stumpy/devicetree.cb

@@ -116,6 +116,9 @@ chip northbridge/intel/sandybridge
 					end # Mouse
 					device pnp 2e.a off end # IR
 				end
+				chip drivers/pc80/tpm
+					device pnp 0c31.0 on end
+				end
 			end
 			device pci 1f.2 on end # SATA Controller 1
 			device pci 1f.3 on end # SMBus