soc/amd/sabrina/fch: enable XTAL pad disabling in S0i3

Switching off the pads of the internal crystal oscillator that connect
to the crystal on the board in S0i3 saves a little power, so enable it.
No measurements to quantify the power savings have been made. PPR #57243
revision 1.59 was used as a reference.

BUG=b:237647468
TEST=None

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I52f14ae5c614ad8ff0479b619de7164afa1e7648
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66336
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>

src/soc/amd/sabrina/fch.c

@@ -178,6 +178,7 @@ static void cgpll_clock_gate_init(void)
 	t = misc_read32(MISC_CLKGATEDCNTL);
 	t |= ALINKCLK_GATEOFFEN;
 	t |= BLINKCLK_GATEOFFEN;
+	t |= XTAL_PAD_S0I3_TURNOFF_EN;
 	t |= XTAL_PAD_S3_TURNOFF_EN;
 	t |= XTAL_PAD_S5_TURNOFF_EN;
 	misc_write32(MISC_CLKGATEDCNTL, t);

src/soc/amd/sabrina/include/soc/southbridge.h

@@ -105,6 +105,7 @@
 #define MISC_CLKGATEDCNTL		0x2c
 #define   ALINKCLK_GATEOFFEN		BIT(16)
 #define   BLINKCLK_GATEOFFEN		BIT(17)
+#define   XTAL_PAD_S0I3_TURNOFF_EN	BIT(19)
 #define   XTAL_PAD_S3_TURNOFF_EN	BIT(20)
 #define   XTAL_PAD_S5_TURNOFF_EN	BIT(21)
 #define MISC_CGPLL_CONFIGURATION0	0x30