missed cache_as_ram_auto.c
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1983 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Yinghai Lu
parent
13f1c2af8b
commit
304f24c2d2
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@ -0,0 +1,228 @@
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/* (c) 2005 Linux Networx GPL see COPYING for details */
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/cardbus.h>
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/* I don't think this code is quite correct but it is close.
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* Anyone with a cardbus bridge and a little time should be able
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* to make it usable quickly. -- Eric Biederman 24 March 2005
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*/
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/*
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* IO should be max 256 bytes. However, since we may
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* have a P2P bridge below a cardbus bridge, we need 4K.
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*/
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#define CARDBUS_IO_SIZE (4096)
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#define CARDBUS_MEM_SIZE (32*1024*1024)
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static void cardbus_record_bridge_resource(
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device_t dev, resource_t moving, resource_t min_size,
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unsigned index, unsigned long type)
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{
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/* Initiliaze the constraints on the current bus */
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struct resource *resource;
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resource = 0;
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if (moving) {
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unsigned long gran;
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resource_t step;
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resource = new_resource(dev, index);
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resource->size = 0;
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gran = 0;
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step = 1;
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while((moving & step) == 0) {
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gran += 1;
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step <<= 1;
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}
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resource->gran = gran;
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resource->align = gran;
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resource->limit = moving | (step - 1);
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resource->flags = type;
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/* Don't let the minimum size exceed what we
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* can put in the resource.
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*/
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if ((min_size - 1) > resource->limit) {
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min_size = resource->limit + 1;
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}
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resource->size = min_size;
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}
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return;
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}
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static void cardbus_size_bridge_resource(device_t dev, unsigned index)
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{
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struct resource *resource;
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resource_t min_size;
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resource = find_resource(dev, index);
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if (resource) {
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min_size = resource->size;
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compute_allocate_resource(&dev->link[0], resource,
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resource->flags, resource->flags);
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/* Allways allocate at least the miniumum size to a
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* cardbus bridge in case a new card is plugged in.
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*/
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if (resource->size < min_size) {
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resource->size = min_size;
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}
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}
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}
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void cardbus_read_resources(device_t dev)
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{
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resource_t moving_base, moving_limit, moving;
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unsigned long type;
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uint16_t ctl;
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/* See which bridge I/O resources are implemented */
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moving_base = pci_moving_config32(dev, PCI_CB_IO_BASE_0);
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moving_limit = pci_moving_config32(dev, PCI_CB_IO_LIMIT_0);
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moving = moving_base & moving_limit;
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/* Initialize the io space constraints on the current bus */
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cardbus_record_bridge_resource(dev, moving, CARDBUS_IO_SIZE,
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PCI_CB_IO_BASE_0, IORESOURCE_IO);
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cardbus_size_bridge_resource(dev, PCI_CB_IO_BASE_0);
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/* See which bridge I/O resources are implemented */
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moving_base = pci_moving_config32(dev, PCI_CB_IO_BASE_1);
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moving_limit = pci_moving_config32(dev, PCI_CB_IO_LIMIT_1);
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moving = moving_base & moving_limit;
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/* Initialize the io space constraints on the current bus */
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cardbus_record_bridge_resource(dev, moving, CARDBUS_IO_SIZE,
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PCI_CB_IO_BASE_1, IORESOURCE_IO);
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/* If I can enable prefetch for mem0 */
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ctl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL);
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ctl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
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ctl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
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ctl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
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pci_write_config16(dev, PCI_CB_BRIDGE_CONTROL, ctl);
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ctl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL);
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/* See which bridge memory resources are implemented */
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moving_base = pci_moving_config32(dev, PCI_CB_MEMORY_BASE_0);
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moving_limit = pci_moving_config32(dev, PCI_CB_MEMORY_LIMIT_0);
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moving = moving_base & moving_limit;
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/* Initialize the memory space constraints on the current bus */
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type = IORESOURCE_MEM;
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if (ctl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
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type |= IORESOURCE_PREFETCH;
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}
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cardbus_record_bridge_resource(dev, moving, CARDBUS_MEM_SIZE,
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PCI_CB_MEMORY_BASE_0, type);
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if (type & IORESOURCE_PREFETCH) {
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cardbus_size_bridge_resource(dev, PCI_CB_MEMORY_BASE_0);
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}
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/* See which bridge memory resources are implemented */
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moving_base = pci_moving_config32(dev, PCI_CB_MEMORY_BASE_1);
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moving_limit = pci_moving_config32(dev, PCI_CB_MEMORY_LIMIT_1);
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moving = moving_base & moving_limit;
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/* Initialize the memory space constraints on the current bus */
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cardbus_record_bridge_resource(dev, moving, CARDBUS_MEM_SIZE,
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PCI_CB_MEMORY_BASE_1, IORESOURCE_MEM);
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cardbus_size_bridge_resource(dev, PCI_CB_MEMORY_BASE_1);
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compact_resources(dev);
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}
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void cardbus_enable_resources(device_t dev)
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{
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uint16_t ctrl;
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ctrl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL);
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ctrl |= (dev->link[0].bridge_ctrl & (
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PCI_BRIDGE_CTL_PARITY |
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PCI_BRIDGE_CTL_SERR |
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PCI_BRIDGE_CTL_NO_ISA |
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PCI_BRIDGE_CTL_VGA |
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PCI_BRIDGE_CTL_MASTER_ABORT |
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PCI_BRIDGE_CTL_BUS_RESET));
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ctrl |= (PCI_CB_BRIDGE_CTL_PARITY + PCI_CB_BRIDGE_CTL_SERR); /* error check */
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printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
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pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
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pci_dev_enable_resources(dev);
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enable_childrens_resources(dev);
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}
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unsigned int cardbus_scan_bus(struct bus *bus,
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unsigned min_devfn, unsigned max_devfn,
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unsigned int max)
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{
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return pci_scan_bus(bus, min_devfn, max_devfn, max);
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}
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unsigned int cardbus_scan_bridge(device_t dev, unsigned int max)
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{
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struct bus *bus;
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uint32_t buses;
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uint16_t cr;
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printk_spew("%s for %s\n", __func__, dev_path(dev));
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bus = &dev->link[0];
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bus->dev = dev;
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dev->links = 1;
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/* Set up the primary, secondary and subordinate bus numbers. We have
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* no idea how many buses are behind this bridge yet, so we set the
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* subordinate bus number to 0xff for the moment.
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*/
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bus->secondary = ++max;
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bus->subordinate = 0xff;
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/* Clear all status bits and turn off memory, I/O and master enables. */
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cr = pci_read_config16(dev, PCI_COMMAND);
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pci_write_config16(dev, PCI_COMMAND, 0x0000);
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pci_write_config16(dev, PCI_STATUS, 0xffff);
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/*
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* Read the existing primary/secondary/subordinate bus
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* number configuration.
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*/
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buses = pci_read_config32(dev, PCI_CB_PRIMARY_BUS);
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/* Configure the bus numbers for this bridge: the configuration
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* transactions will not be propagated by the bridge if it is not
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* correctly configured.
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*/
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buses &= 0xff000000;
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buses |= (((unsigned int) (dev->bus->secondary) << 0) |
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((unsigned int) (bus->secondary) << 8) |
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((unsigned int) (bus->subordinate) << 16));
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pci_write_config32(dev, PCI_CB_PRIMARY_BUS, buses);
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/* Now we can scan all subordinate buses
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* i.e. the bus behind the bridge.
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*/
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max = cardbus_scan_bus(bus, 0x00, 0xff, max);
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/* We know the number of buses behind this bridge. Set the subordinate
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* bus number to its real value.
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*/
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bus->subordinate = max;
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buses = (buses & 0xff00ffff) |
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((unsigned int) (bus->subordinate) << 16);
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pci_write_config32(dev, PCI_CB_PRIMARY_BUS, buses);
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pci_write_config16(dev, PCI_COMMAND, cr);
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printk_spew("%s returns max %d\n", __func__, max);
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return max;
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}
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struct device_operations default_cardbus_ops_bus = {
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.read_resources = cardbus_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = cardbus_enable_resources,
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.init = 0,
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.scan_bus = cardbus_scan_bridge,
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.enable = 0,
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.reset_bus = pci_bus_reset,
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};
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@ -0,0 +1,398 @@
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#define ASSEMBLY 1
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#define __ROMCC__
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <arch/romcc_io.h>
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#include <cpu/x86/lapic.h>
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#include "option_table.h"
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#include "pc80/mc146818rtc_early.c"
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#include "northbridge/amd/amdk8/cpu_rev.c"
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#define K8_HT_FREQ_1G_SUPPORT 0
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#include "northbridge/amd/amdk8/incoherent_ht.c"
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#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
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#include "northbridge/amd/amdk8/raminit.h"
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#include "cpu/amd/model_fxx/apic_timer.c"
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#include "lib/delay.c"
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#if CONFIG_USE_INIT == 0
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#include "lib/memcpy.c"
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#endif
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#include "cpu/x86/lapic/boot_cpu.c"
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#include "northbridge/amd/amdk8/reset_test.c"
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#include "northbridge/amd/amdk8/debug.c"
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#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
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#include "cpu/amd/mtrr/amd_earlymtrr.c"
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#include "cpu/x86/bist.h"
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#include "northbridge/amd/amdk8/setup_resource_map.c"
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#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
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/* Look up a which bus a given node/link combination is on.
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* return 0 when we can't find the answer.
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*/
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static unsigned node_link_to_bus(unsigned node, unsigned link)
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{
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unsigned reg;
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for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
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unsigned config_map;
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config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
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if ((config_map & 3) != 3) {
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continue;
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}
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if ((((config_map >> 4) & 7) == node) &&
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(((config_map >> 8) & 3) == link))
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{
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return (config_map >> 16) & 0xff;
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}
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}
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return 0;
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}
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static void hard_reset(void)
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{
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device_t dev;
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/* Find the device */
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dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3);
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set_bios_reset();
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/* enable cf9 */
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pci_write_config8(dev, 0x41, 0xf1);
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/* reset */
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outb(0x0e, 0x0cf9);
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}
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static void soft_reset(void)
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{
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device_t dev;
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/* Find the device */
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dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0);
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set_bios_reset();
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pci_write_config8(dev, 0x47, 1);
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}
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static void memreset_setup(void)
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{
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if (is_cpu_pre_c0()) {
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
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}
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else {
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
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}
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
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}
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static void memreset(int controllers, const struct mem_controller *ctrl)
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{
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if (is_cpu_pre_c0()) {
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udelay(800);
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outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
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udelay(90);
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}
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}
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static inline void activate_spd_rom(const struct mem_controller *ctrl)
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{
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/* nothing to do */
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}
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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return smbus_read_byte(device, address);
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}
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#define K8_4RANK_DIMM_SUPPORT 1
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#include "northbridge/amd/amdk8/raminit.c"
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#include "northbridge/amd/amdk8/resourcemap.c"
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#include "northbridge/amd/amdk8/coherent_ht.c"
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#include "sdram/generic_sdram.c"
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#if CONFIG_LOGICAL_CPUS==1
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#define SET_NB_CFG_54 1
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#include "cpu/amd/dualcore/dualcore.c"
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#else
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#include "cpu/amd/model_fxx/node_id.c"
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#endif
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#include "cpu/amd/car/copy_and_run.c"
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#if USE_FALLBACK_IMAGE == 1
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#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
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#include "northbridge/amd/amdk8/early_ht.c"
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void real_main(unsigned long bist);
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void amd64_main(unsigned long bist)
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{
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#if CONFIG_LOGICAL_CPUS==1
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struct node_core_id id;
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#else
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unsigned nodeid;
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#endif
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/* Make cerain my local apic is useable */
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// enable_lapic();
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#if CONFIG_LOGICAL_CPUS==1
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id = get_node_core_id_x();
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/* Is this a cpu only reset? */
|
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if (cpu_init_detected(id.nodeid)) {
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#else
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// nodeid = lapicid();
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nodeid = get_node_id();
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/* Is this a cpu only reset? */
|
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if (cpu_init_detected(nodeid)) {
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#endif
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if (last_boot_normal()) {
|
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goto normal_image;
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} else {
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goto cpu_reset;
|
||||
}
|
||||
}
|
||||
|
||||
/* Is this a secondary cpu? */
|
||||
if (!boot_cpu()) {
|
||||
if (last_boot_normal()) {
|
||||
goto normal_image;
|
||||
} else {
|
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goto fallback_image;
|
||||
}
|
||||
}
|
||||
|
||||
/* Nothing special needs to be done to find bus 0 */
|
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/* Allow the HT devices to be found */
|
||||
|
||||
enumerate_ht_chain();
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||||
|
||||
/* Setup the ck804 */
|
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amd8111_enable_rom();
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|
||||
/* Is this a deliberate reset by the bios */
|
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if (bios_reset_detected() && last_boot_normal()) {
|
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goto normal_image;
|
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}
|
||||
/* This is the primary cpu how should I boot? */
|
||||
else if (do_normal_boot()) {
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goto normal_image;
|
||||
}
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||||
else {
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goto fallback_image;
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||||
}
|
||||
normal_image:
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||||
__asm__ volatile ("jmp __normal_image"
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||||
: /* outputs */
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||||
: "a" (bist) /* inputs */
|
||||
);
|
||||
cpu_reset:
|
||||
#if 0
|
||||
//CPU reset will reset memtroller ???
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||||
asm volatile ("jmp __cpu_reset"
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||||
: /* outputs */
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||||
: "a"(bist) /* inputs */
|
||||
);
|
||||
#endif
|
||||
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||||
fallback_image:
|
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real_main(bist);
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}
|
||||
void real_main(unsigned long bist)
|
||||
#else
|
||||
void amd64_main(unsigned long bist)
|
||||
#endif
|
||||
{
|
||||
static const struct mem_controller cpu[] = {
|
||||
{
|
||||
.node_id = 0,
|
||||
.f0 = PCI_DEV(0, 0x18, 0),
|
||||
.f1 = PCI_DEV(0, 0x18, 1),
|
||||
.f2 = PCI_DEV(0, 0x18, 2),
|
||||
.f3 = PCI_DEV(0, 0x18, 3),
|
||||
.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
|
||||
.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
|
||||
},
|
||||
};
|
||||
|
||||
int needs_reset;
|
||||
unsigned cpu_reset = 0;
|
||||
|
||||
if (bist == 0) {
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
struct node_core_id id;
|
||||
#else
|
||||
unsigned nodeid;
|
||||
#endif
|
||||
/* Skip this if there was a built in self test failure */
|
||||
// amd_early_mtrr_init(); # don't need, already done in cache_as_ram
|
||||
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
set_apicid_cpuid_lo();
|
||||
id = get_node_core_id_x(); // that is initid
|
||||
#else
|
||||
nodeid = get_node_id();
|
||||
#endif
|
||||
|
||||
enable_lapic();
|
||||
init_timer();
|
||||
|
||||
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
if(id.coreid == 0) {
|
||||
if (cpu_init_detected(id.nodeid)) {
|
||||
cpu_reset = 1;
|
||||
goto cpu_reset_x;
|
||||
}
|
||||
distinguish_cpu_resets(id.nodeid);
|
||||
}
|
||||
#else
|
||||
if (cpu_init_detected(nodeid)) {
|
||||
cpu_reset = 1;
|
||||
goto cpu_reset_x;
|
||||
}
|
||||
distinguish_cpu_resets(nodeid);
|
||||
#endif
|
||||
|
||||
|
||||
if (!boot_cpu()
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
|| (id.coreid != 0)
|
||||
#endif
|
||||
) {
|
||||
// We need stop the CACHE as RAM for this CPU too
|
||||
#include "cpu/amd/car/cache_as_ram_post.c"
|
||||
stop_this_cpu(); // it will stop all cores except core0 of cpu0
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
|
||||
uart_init();
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
setup_default_resource_map();
|
||||
#if 0
|
||||
dump_pci_device(PCI_DEV(0, 0x18, 0));
|
||||
dump_pci_device(PCI_DEV(0, 0x19, 0));
|
||||
#endif
|
||||
|
||||
needs_reset = setup_coherent_ht_domain();
|
||||
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
// It is said that we should start core1 after all core0 launched
|
||||
start_other_cores();
|
||||
#endif
|
||||
needs_reset |= ht_setup_chains_x();
|
||||
|
||||
if (needs_reset) {
|
||||
print_info("ht reset -\r\n");
|
||||
soft_reset();
|
||||
}
|
||||
|
||||
enable_smbus();
|
||||
|
||||
memreset_setup();
|
||||
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
|
||||
|
||||
|
||||
#if 1
|
||||
{
|
||||
/* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
|
||||
unsigned v_esp;
|
||||
__asm__ volatile (
|
||||
"movl %%esp, %0\n\t"
|
||||
: "=a" (v_esp)
|
||||
);
|
||||
#if CONFIG_USE_INIT
|
||||
printk_debug("v_esp=%08x\r\n", v_esp);
|
||||
#else
|
||||
print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#if 1
|
||||
|
||||
|
||||
cpu_reset_x:
|
||||
|
||||
#if CONFIG_USE_INIT
|
||||
printk_debug("cpu_reset = %08x\r\n",cpu_reset);
|
||||
#else
|
||||
print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
|
||||
#endif
|
||||
|
||||
if(cpu_reset == 0) {
|
||||
print_debug("Clearing initial memory region: ");
|
||||
}
|
||||
print_debug("No cache as ram now - ");
|
||||
|
||||
/* store cpu_reset to ebx */
|
||||
__asm__ volatile (
|
||||
"movl %0, %%ebx\n\t"
|
||||
::"a" (cpu_reset)
|
||||
);
|
||||
|
||||
if(cpu_reset==0) {
|
||||
#define CLEAR_FIRST_1M_RAM 1
|
||||
#include "cpu/amd/car/cache_as_ram_post.c"
|
||||
}
|
||||
else {
|
||||
#undef CLEAR_FIRST_1M_RAM
|
||||
#include "cpu/amd/car/cache_as_ram_post.c"
|
||||
}
|
||||
|
||||
__asm__ volatile (
|
||||
/* set new esp */ /* before _RAMBASE */
|
||||
"subl %0, %%ebp\n\t"
|
||||
"subl %0, %%esp\n\t"
|
||||
::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE )
|
||||
);
|
||||
|
||||
{
|
||||
unsigned new_cpu_reset;
|
||||
|
||||
/* get back cpu_reset from ebx */
|
||||
__asm__ volatile (
|
||||
"movl %%ebx, %0\n\t"
|
||||
:"=a" (new_cpu_reset)
|
||||
);
|
||||
|
||||
print_debug("Use Ram as Stack now - "); /* but We can not go back any more, we lost old stack data in cache as ram*/
|
||||
if(new_cpu_reset==0) {
|
||||
print_debug("done\r\n");
|
||||
} else
|
||||
{
|
||||
print_debug("\r\n");
|
||||
}
|
||||
|
||||
#if CONFIG_USE_INIT
|
||||
printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset);
|
||||
#else
|
||||
print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
|
||||
#endif
|
||||
/*copy and execute linuxbios_ram */
|
||||
copy_and_run(new_cpu_reset);
|
||||
/* We will not return */
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
print_debug("should not be here -\r\n");
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,413 @@
|
|||
#define ASSEMBLY 1
|
||||
#define __ROMCC__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <arch/romcc_io.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include "option_table.h"
|
||||
#include "pc80/mc146818rtc_early.c"
|
||||
#include "pc80/serial.c"
|
||||
#include "arch/i386/lib/console.c"
|
||||
#include "ram/ramtest.c"
|
||||
|
||||
#include "northbridge/amd/amdk8/cpu_rev.c"
|
||||
#define K8_HT_FREQ_1G_SUPPORT 0
|
||||
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
||||
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
|
||||
#include "northbridge/amd/amdk8/raminit.h"
|
||||
#include "cpu/amd/model_fxx/apic_timer.c"
|
||||
#include "lib/delay.c"
|
||||
|
||||
#if CONFIG_USE_INIT == 0
|
||||
#include "lib/memcpy.c"
|
||||
#endif
|
||||
|
||||
#include "cpu/x86/lapic/boot_cpu.c"
|
||||
#include "northbridge/amd/amdk8/reset_test.c"
|
||||
#include "northbridge/amd/amdk8/debug.c"
|
||||
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
|
||||
|
||||
#include "cpu/amd/mtrr/amd_earlymtrr.c"
|
||||
#include "cpu/x86/bist.h"
|
||||
|
||||
#include "northbridge/amd/amdk8/setup_resource_map.c"
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
|
||||
|
||||
/* Look up a which bus a given node/link combination is on.
|
||||
* return 0 when we can't find the answer.
|
||||
*/
|
||||
static unsigned node_link_to_bus(unsigned node, unsigned link)
|
||||
{
|
||||
unsigned reg;
|
||||
|
||||
for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
|
||||
unsigned config_map;
|
||||
config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
|
||||
if ((config_map & 3) != 3) {
|
||||
continue;
|
||||
}
|
||||
if ((((config_map >> 4) & 7) == node) &&
|
||||
(((config_map >> 8) & 3) == link))
|
||||
{
|
||||
return (config_map >> 16) & 0xff;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void hard_reset(void)
|
||||
{
|
||||
device_t dev;
|
||||
|
||||
/* Find the device */
|
||||
dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3);
|
||||
|
||||
set_bios_reset();
|
||||
|
||||
/* enable cf9 */
|
||||
pci_write_config8(dev, 0x41, 0xf1);
|
||||
/* reset */
|
||||
outb(0x0e, 0x0cf9);
|
||||
}
|
||||
|
||||
static void soft_reset(void)
|
||||
{
|
||||
device_t dev;
|
||||
|
||||
/* Find the device */
|
||||
dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0);
|
||||
|
||||
set_bios_reset();
|
||||
pci_write_config8(dev, 0x47, 1);
|
||||
}
|
||||
|
||||
static void memreset_setup(void)
|
||||
{
|
||||
if (is_cpu_pre_c0()) {
|
||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
|
||||
}
|
||||
else {
|
||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
|
||||
}
|
||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
|
||||
}
|
||||
|
||||
static void memreset(int controllers, const struct mem_controller *ctrl)
|
||||
{
|
||||
if (is_cpu_pre_c0()) {
|
||||
udelay(800);
|
||||
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
|
||||
udelay(90);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void activate_spd_rom(const struct mem_controller *ctrl)
|
||||
{
|
||||
/* nothing to do */
|
||||
}
|
||||
|
||||
static inline int spd_read_byte(unsigned device, unsigned address)
|
||||
{
|
||||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
#define K8_4RANK_DIMM_SUPPORT 1
|
||||
|
||||
#include "northbridge/amd/amdk8/raminit.c"
|
||||
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||
#include "sdram/generic_sdram.c"
|
||||
#include "northbridge/amd/amdk8/resourcemap.c"
|
||||
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
#define SET_NB_CFG_54 1
|
||||
#include "cpu/amd/dualcore/dualcore.c"
|
||||
#else
|
||||
#include "cpu/amd/model_fxx/node_id.c"
|
||||
#endif
|
||||
|
||||
#define FIRST_CPU 1
|
||||
#define SECOND_CPU 1
|
||||
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
|
||||
|
||||
#include "cpu/amd/car/copy_and_run.c"
|
||||
|
||||
#if USE_FALLBACK_IMAGE == 1
|
||||
|
||||
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
|
||||
#include "northbridge/amd/amdk8/early_ht.c"
|
||||
|
||||
void real_main(unsigned long bist);
|
||||
|
||||
void amd64_main(unsigned long bist)
|
||||
{
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
struct node_core_id id;
|
||||
#else
|
||||
unsigned nodeid;
|
||||
#endif
|
||||
/* Make cerain my local apic is useable */
|
||||
// enable_lapic();
|
||||
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
id = get_node_core_id_x();
|
||||
/* Is this a cpu only reset? */
|
||||
if (cpu_init_detected(id.nodeid)) {
|
||||
#else
|
||||
// nodeid = lapicid();
|
||||
nodeid = get_node_id();
|
||||
/* Is this a cpu only reset? */
|
||||
if (cpu_init_detected(nodeid)) {
|
||||
#endif
|
||||
if (last_boot_normal()) {
|
||||
goto normal_image;
|
||||
} else {
|
||||
goto cpu_reset;
|
||||
}
|
||||
}
|
||||
|
||||
/* Is this a secondary cpu? */
|
||||
if (!boot_cpu()) {
|
||||
if (last_boot_normal()) {
|
||||
goto normal_image;
|
||||
} else {
|
||||
goto fallback_image;
|
||||
}
|
||||
}
|
||||
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
|
||||
enumerate_ht_chain();
|
||||
|
||||
amd8111_enable_rom();
|
||||
|
||||
/* Is this a deliberate reset by the bios */
|
||||
if (bios_reset_detected() && last_boot_normal()) {
|
||||
goto normal_image;
|
||||
}
|
||||
/* This is the primary cpu how should I boot? */
|
||||
else if (do_normal_boot()) {
|
||||
goto normal_image;
|
||||
}
|
||||
else {
|
||||
goto fallback_image;
|
||||
}
|
||||
normal_image:
|
||||
__asm__ volatile ("jmp __normal_image"
|
||||
: /* outputs */
|
||||
: "a" (bist) /* inputs */
|
||||
);
|
||||
cpu_reset:
|
||||
#if 0
|
||||
//CPU reset will reset memtroller ???
|
||||
asm volatile ("jmp __cpu_reset"
|
||||
: /* outputs */
|
||||
: "a"(bist) /* inputs */
|
||||
);
|
||||
#endif
|
||||
|
||||
fallback_image:
|
||||
real_main(bist);
|
||||
}
|
||||
void real_main(unsigned long bist)
|
||||
#else
|
||||
void amd64_main(unsigned long bist)
|
||||
#endif
|
||||
{
|
||||
static const struct mem_controller cpu[] = {
|
||||
#if FIRST_CPU
|
||||
{
|
||||
.node_id = 0,
|
||||
.f0 = PCI_DEV(0, 0x18, 0),
|
||||
.f1 = PCI_DEV(0, 0x18, 1),
|
||||
.f2 = PCI_DEV(0, 0x18, 2),
|
||||
.f3 = PCI_DEV(0, 0x18, 3),
|
||||
.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
|
||||
.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
|
||||
},
|
||||
#endif
|
||||
#if SECOND_CPU
|
||||
{
|
||||
.node_id = 1,
|
||||
.f0 = PCI_DEV(0, 0x19, 0),
|
||||
.f1 = PCI_DEV(0, 0x19, 1),
|
||||
.f2 = PCI_DEV(0, 0x19, 2),
|
||||
.f3 = PCI_DEV(0, 0x19, 3),
|
||||
.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
|
||||
.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
int needs_reset;
|
||||
unsigned cpu_reset = 0;
|
||||
|
||||
if (bist == 0) {
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
struct node_core_id id;
|
||||
#else
|
||||
unsigned nodeid;
|
||||
#endif
|
||||
/* Skip this if there was a built in self test failure */
|
||||
// amd_early_mtrr_init(); # don't need, already done in cache_as_ram
|
||||
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
set_apicid_cpuid_lo();
|
||||
id = get_node_core_id_x(); // that is initid
|
||||
#else
|
||||
nodeid = get_node_id();
|
||||
#endif
|
||||
|
||||
enable_lapic();
|
||||
init_timer();
|
||||
|
||||
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
if(id.coreid == 0) {
|
||||
if (cpu_init_detected(id.nodeid)) {
|
||||
// __asm__ volatile ("jmp __cpu_reset");
|
||||
cpu_reset = 1;
|
||||
goto cpu_reset_x;
|
||||
}
|
||||
distinguish_cpu_resets(id.nodeid);
|
||||
// start_other_core(id.nodeid);
|
||||
}
|
||||
#else
|
||||
if (cpu_init_detected(nodeid)) {
|
||||
// __asm__ volatile ("jmp __cpu_reset");
|
||||
cpu_reset = 1;
|
||||
goto cpu_reset_x;
|
||||
}
|
||||
distinguish_cpu_resets(nodeid);
|
||||
#endif
|
||||
|
||||
|
||||
if (!boot_cpu()
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
|| (id.coreid != 0)
|
||||
#endif
|
||||
) {
|
||||
// We need stop the CACHE as RAM for this CPU too
|
||||
#include "cpu/amd/car/cache_as_ram_post.c"
|
||||
stop_this_cpu(); // it will stop all cores except core0 of cpu0
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
|
||||
uart_init();
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
setup_default_resource_map();
|
||||
|
||||
needs_reset = setup_coherent_ht_domain();
|
||||
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
start_other_cores();
|
||||
#endif
|
||||
needs_reset |= ht_setup_chains_x();
|
||||
|
||||
if (needs_reset) {
|
||||
print_info("ht reset -\r\n");
|
||||
soft_reset();
|
||||
}
|
||||
|
||||
enable_smbus();
|
||||
|
||||
memreset_setup();
|
||||
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
|
||||
|
||||
|
||||
#if 1
|
||||
{
|
||||
/* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
|
||||
unsigned v_esp;
|
||||
__asm__ volatile (
|
||||
"movl %%esp, %0\n\t"
|
||||
: "=a" (v_esp)
|
||||
);
|
||||
#if CONFIG_USE_INIT
|
||||
printk_debug("v_esp=%08x\r\n", v_esp);
|
||||
#else
|
||||
print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#if 1
|
||||
|
||||
|
||||
cpu_reset_x:
|
||||
|
||||
#if CONFIG_USE_INIT
|
||||
printk_debug("cpu_reset = %08x\r\n",cpu_reset);
|
||||
#else
|
||||
print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
|
||||
#endif
|
||||
|
||||
if(cpu_reset == 0) {
|
||||
print_debug("Clearing initial memory region: ");
|
||||
}
|
||||
print_debug("No cache as ram now - ");
|
||||
|
||||
/* store cpu_reset to ebx */
|
||||
__asm__ volatile (
|
||||
"movl %0, %%ebx\n\t"
|
||||
::"a" (cpu_reset)
|
||||
);
|
||||
|
||||
if(cpu_reset==0) {
|
||||
#define CLEAR_FIRST_1M_RAM 1
|
||||
#include "cpu/amd/car/cache_as_ram_post.c"
|
||||
}
|
||||
else {
|
||||
#undef CLEAR_FIRST_1M_RAM
|
||||
#include "cpu/amd/car/cache_as_ram_post.c"
|
||||
}
|
||||
|
||||
__asm__ volatile (
|
||||
/* set new esp */ /* before _RAMBASE */
|
||||
"subl %0, %%ebp\n\t"
|
||||
"subl %0, %%esp\n\t"
|
||||
::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE )
|
||||
);
|
||||
|
||||
{
|
||||
unsigned new_cpu_reset;
|
||||
|
||||
/* get back cpu_reset from ebx */
|
||||
__asm__ volatile (
|
||||
"movl %%ebx, %0\n\t"
|
||||
:"=a" (new_cpu_reset)
|
||||
);
|
||||
|
||||
print_debug("Use Ram as Stack now - "); /* but We can not go back any more, we lost old stack data in cache as ram*/
|
||||
if(new_cpu_reset==0) {
|
||||
print_debug("done\r\n");
|
||||
} else
|
||||
{
|
||||
print_debug("\r\n");
|
||||
}
|
||||
|
||||
#if CONFIG_USE_INIT
|
||||
printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset);
|
||||
#else
|
||||
print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
|
||||
#endif
|
||||
/*copy and execute linuxbios_ram */
|
||||
copy_and_run(new_cpu_reset);
|
||||
/* We will not return */
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
print_debug("should not be here -\r\n");
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,409 @@
|
|||
#define ASSEMBLY 1
|
||||
#define __ROMCC__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <arch/romcc_io.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include "option_table.h"
|
||||
#include "pc80/mc146818rtc_early.c"
|
||||
#include "pc80/serial.c"
|
||||
#include "arch/i386/lib/console.c"
|
||||
#include "ram/ramtest.c"
|
||||
|
||||
#include "northbridge/amd/amdk8/cpu_rev.c"
|
||||
#define K8_HT_FREQ_1G_SUPPORT 0
|
||||
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
||||
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
|
||||
#include "northbridge/amd/amdk8/raminit.h"
|
||||
#include "cpu/amd/model_fxx/apic_timer.c"
|
||||
#include "lib/delay.c"
|
||||
|
||||
#if CONFIG_USE_INIT == 0
|
||||
#include "lib/memcpy.c"
|
||||
#endif
|
||||
|
||||
#include "cpu/x86/lapic/boot_cpu.c"
|
||||
#include "northbridge/amd/amdk8/reset_test.c"
|
||||
#include "northbridge/amd/amdk8/debug.c"
|
||||
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
|
||||
|
||||
#include "cpu/amd/mtrr/amd_earlymtrr.c"
|
||||
#include "cpu/x86/bist.h"
|
||||
|
||||
#include "northbridge/amd/amdk8/setup_resource_map.c"
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
|
||||
/* Look up a which bus a given node/link combination is on.
|
||||
* return 0 when we can't find the answer.
|
||||
*/
|
||||
static unsigned node_link_to_bus(unsigned node, unsigned link)
|
||||
{
|
||||
unsigned reg;
|
||||
|
||||
for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
|
||||
unsigned config_map;
|
||||
config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
|
||||
if ((config_map & 3) != 3) {
|
||||
continue;
|
||||
}
|
||||
if ((((config_map >> 4) & 7) == node) &&
|
||||
(((config_map >> 8) & 3) == link))
|
||||
{
|
||||
return (config_map >> 16) & 0xff;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void hard_reset(void)
|
||||
{
|
||||
device_t dev;
|
||||
|
||||
/* Find the device */
|
||||
dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3);
|
||||
|
||||
set_bios_reset();
|
||||
|
||||
/* enable cf9 */
|
||||
pci_write_config8(dev, 0x41, 0xf1);
|
||||
/* reset */
|
||||
outb(0x0e, 0x0cf9);
|
||||
}
|
||||
|
||||
static void soft_reset(void)
|
||||
{
|
||||
device_t dev;
|
||||
|
||||
/* Find the device */
|
||||
dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0);
|
||||
|
||||
set_bios_reset();
|
||||
pci_write_config8(dev, 0x47, 1);
|
||||
}
|
||||
|
||||
static void memreset_setup(void)
|
||||
{
|
||||
if (is_cpu_pre_c0()) {
|
||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
|
||||
}
|
||||
else {
|
||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
|
||||
}
|
||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
|
||||
}
|
||||
|
||||
static void memreset(int controllers, const struct mem_controller *ctrl)
|
||||
{
|
||||
if (is_cpu_pre_c0()) {
|
||||
udelay(800);
|
||||
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
|
||||
udelay(90);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void activate_spd_rom(const struct mem_controller *ctrl)
|
||||
{
|
||||
/* nothing to do */
|
||||
}
|
||||
|
||||
static inline int spd_read_byte(unsigned device, unsigned address)
|
||||
{
|
||||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
#define K8_4RANK_DIMM_SUPPORT 1
|
||||
|
||||
#include "northbridge/amd/amdk8/raminit.c"
|
||||
#include "northbridge/amd/amdk8/resourcemap.c"
|
||||
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||
#include "sdram/generic_sdram.c"
|
||||
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
#define SET_NB_CFG_54 1
|
||||
#include "cpu/amd/dualcore/dualcore.c"
|
||||
#else
|
||||
#include "cpu/amd/model_fxx/node_id.c"
|
||||
#endif
|
||||
|
||||
#define FIRST_CPU 1
|
||||
#define SECOND_CPU 1
|
||||
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
|
||||
|
||||
#include "cpu/amd/car/copy_and_run.c"
|
||||
|
||||
#if USE_FALLBACK_IMAGE == 1
|
||||
|
||||
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
|
||||
#include "northbridge/amd/amdk8/early_ht.c"
|
||||
|
||||
void real_main(unsigned long bist);
|
||||
|
||||
void amd64_main(unsigned long bist)
|
||||
{
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
struct node_core_id id;
|
||||
#else
|
||||
unsigned nodeid;
|
||||
#endif
|
||||
/* Make cerain my local apic is useable */
|
||||
// enable_lapic();
|
||||
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
id = get_node_core_id_x();
|
||||
/* Is this a cpu only reset? */
|
||||
if (cpu_init_detected(id.nodeid)) {
|
||||
#else
|
||||
// nodeid = lapicid();
|
||||
nodeid = get_node_id();
|
||||
/* Is this a cpu only reset? */
|
||||
if (cpu_init_detected(nodeid)) {
|
||||
#endif
|
||||
if (last_boot_normal()) {
|
||||
goto normal_image;
|
||||
} else {
|
||||
goto cpu_reset;
|
||||
}
|
||||
}
|
||||
|
||||
/* Is this a secondary cpu? */
|
||||
if (!boot_cpu()) {
|
||||
if (last_boot_normal()) {
|
||||
goto normal_image;
|
||||
} else {
|
||||
goto fallback_image;
|
||||
}
|
||||
}
|
||||
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
|
||||
enumerate_ht_chain();
|
||||
|
||||
/* Setup the ck804 */
|
||||
amd8111_enable_rom();
|
||||
|
||||
/* Is this a deliberate reset by the bios */
|
||||
if (bios_reset_detected() && last_boot_normal()) {
|
||||
goto normal_image;
|
||||
}
|
||||
/* This is the primary cpu how should I boot? */
|
||||
else if (do_normal_boot()) {
|
||||
goto normal_image;
|
||||
}
|
||||
else {
|
||||
goto fallback_image;
|
||||
}
|
||||
normal_image:
|
||||
__asm__ volatile ("jmp __normal_image"
|
||||
: /* outputs */
|
||||
: "a" (bist) /* inputs */
|
||||
);
|
||||
cpu_reset:
|
||||
#if 0
|
||||
//CPU reset will reset memtroller ???
|
||||
asm volatile ("jmp __cpu_reset"
|
||||
: /* outputs */
|
||||
: "a"(bist) /* inputs */
|
||||
);
|
||||
#endif
|
||||
|
||||
fallback_image:
|
||||
real_main(bist);
|
||||
}
|
||||
void real_main(unsigned long bist)
|
||||
#else
|
||||
void amd64_main(unsigned long bist)
|
||||
#endif
|
||||
{
|
||||
static const struct mem_controller cpu[] = {
|
||||
#if FIRST_CPU
|
||||
{
|
||||
.node_id = 0,
|
||||
.f0 = PCI_DEV(0, 0x18, 0),
|
||||
.f1 = PCI_DEV(0, 0x18, 1),
|
||||
.f2 = PCI_DEV(0, 0x18, 2),
|
||||
.f3 = PCI_DEV(0, 0x18, 3),
|
||||
.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
|
||||
.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
|
||||
},
|
||||
#endif
|
||||
#if SECOND_CPU
|
||||
{
|
||||
.node_id = 1,
|
||||
.f0 = PCI_DEV(0, 0x19, 0),
|
||||
.f1 = PCI_DEV(0, 0x19, 1),
|
||||
.f2 = PCI_DEV(0, 0x19, 2),
|
||||
.f3 = PCI_DEV(0, 0x19, 3),
|
||||
.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
|
||||
.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
int needs_reset;
|
||||
unsigned cpu_reset = 0;
|
||||
|
||||
if (bist == 0) {
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
struct node_core_id id;
|
||||
#else
|
||||
unsigned nodeid;
|
||||
#endif
|
||||
/* Skip this if there was a built in self test failure */
|
||||
// amd_early_mtrr_init(); # don't need, already done in cache_as_ram
|
||||
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
set_apicid_cpuid_lo();
|
||||
id = get_node_core_id_x(); // that is initid
|
||||
#else
|
||||
nodeid = get_node_id();
|
||||
#endif
|
||||
|
||||
enable_lapic();
|
||||
init_timer();
|
||||
|
||||
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
if(id.coreid == 0) {
|
||||
if (cpu_init_detected(id.nodeid)) {
|
||||
cpu_reset = 1;
|
||||
goto cpu_reset_x;
|
||||
}
|
||||
distinguish_cpu_resets(id.nodeid);
|
||||
}
|
||||
#else
|
||||
if (cpu_init_detected(nodeid)) {
|
||||
cpu_reset = 1;
|
||||
goto cpu_reset_x;
|
||||
}
|
||||
distinguish_cpu_resets(nodeid);
|
||||
#endif
|
||||
|
||||
|
||||
if (!boot_cpu()
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
|| (id.coreid != 0)
|
||||
#endif
|
||||
) {
|
||||
// We need stop the CACHE as RAM for this CPU too
|
||||
#include "cpu/amd/car/cache_as_ram_post.c"
|
||||
stop_this_cpu(); // it will stop all cores except core0 of cpu0
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
|
||||
uart_init();
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
setup_default_resource_map();
|
||||
|
||||
needs_reset = setup_coherent_ht_domain();
|
||||
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
start_other_cores();
|
||||
#endif
|
||||
needs_reset |= ht_setup_chains_x();
|
||||
|
||||
if (needs_reset) {
|
||||
print_info("ht reset -\r\n");
|
||||
soft_reset();
|
||||
}
|
||||
|
||||
enable_smbus();
|
||||
|
||||
memreset_setup();
|
||||
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
|
||||
|
||||
#if 1
|
||||
{
|
||||
/* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
|
||||
unsigned v_esp;
|
||||
__asm__ volatile (
|
||||
"movl %%esp, %0\n\t"
|
||||
: "=a" (v_esp)
|
||||
);
|
||||
#if CONFIG_USE_INIT
|
||||
printk_debug("v_esp=%08x\r\n", v_esp);
|
||||
#else
|
||||
print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#if 1
|
||||
|
||||
|
||||
cpu_reset_x:
|
||||
|
||||
#if CONFIG_USE_INIT
|
||||
printk_debug("cpu_reset = %08x\r\n",cpu_reset);
|
||||
#else
|
||||
print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
|
||||
#endif
|
||||
|
||||
if(cpu_reset == 0) {
|
||||
print_debug("Clearing initial memory region: ");
|
||||
}
|
||||
print_debug("No cache as ram now - ");
|
||||
|
||||
/* store cpu_reset to ebx */
|
||||
__asm__ volatile (
|
||||
"movl %0, %%ebx\n\t"
|
||||
::"a" (cpu_reset)
|
||||
);
|
||||
|
||||
if(cpu_reset==0) {
|
||||
#define CLEAR_FIRST_1M_RAM 1
|
||||
#include "cpu/amd/car/cache_as_ram_post.c"
|
||||
}
|
||||
else {
|
||||
#undef CLEAR_FIRST_1M_RAM
|
||||
#include "cpu/amd/car/cache_as_ram_post.c"
|
||||
}
|
||||
|
||||
__asm__ volatile (
|
||||
/* set new esp */ /* before _RAMBASE */
|
||||
"subl %0, %%ebp\n\t"
|
||||
"subl %0, %%esp\n\t"
|
||||
::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE )
|
||||
);
|
||||
|
||||
{
|
||||
unsigned new_cpu_reset;
|
||||
|
||||
/* get back cpu_reset from ebx */
|
||||
__asm__ volatile (
|
||||
"movl %%ebx, %0\n\t"
|
||||
:"=a" (new_cpu_reset)
|
||||
);
|
||||
|
||||
print_debug("Use Ram as Stack now - "); /* but We can not go back any more, we lost old stack data in cache as ram*/
|
||||
if(new_cpu_reset==0) {
|
||||
print_debug("done\r\n");
|
||||
} else
|
||||
{
|
||||
print_debug("\r\n");
|
||||
}
|
||||
|
||||
#if CONFIG_USE_INIT
|
||||
printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset);
|
||||
#else
|
||||
print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
|
||||
#endif
|
||||
/*copy and execute linuxbios_ram */
|
||||
copy_and_run(new_cpu_reset);
|
||||
/* We will not return */
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
print_debug("should not be here -\r\n");
|
||||
|
||||
}
|
||||
Loading…
Reference in New Issue