mb/google/brya/variants/osiris: Init devicetree for osiris
Init basic override devicetree based on schematics BUG=b:224423318 TEST=FW_NAME="osiris" emerge-brya coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ie69957b39b5c299846c64f67fb29207cf858e50e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64199 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
David Wu
Tim Wawrzynczak
parent
f5319efa84
commit
305086c0f2
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@ -208,6 +208,9 @@ config BOARD_GOOGLE_CRAASK
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config BOARD_GOOGLE_OSIRIS
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config BOARD_GOOGLE_OSIRIS
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bool "-> Osiris"
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bool "-> Osiris"
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select BOARD_GOOGLE_BASEBOARD_BRYA
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select BOARD_GOOGLE_BASEBOARD_BRYA
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select RT8168_GEN_ACPI_POWER_RESOURCE
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select RT8168_GET_MAC_FROM_VPD
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select RT8168_SET_LED_MODE
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config BOARD_GOOGLE_MITHRAX
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config BOARD_GOOGLE_MITHRAX
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bool "-> Mithrax"
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bool "-> Mithrax"
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@ -4,3 +4,5 @@ bootblock-y += gpio.c
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romstage-y += gpio.c
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romstage-y += gpio.c
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ramstage-y += gpio.c
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ramstage-y += gpio.c
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ramstage-$(CONFIG_FW_CONFIG) += variant.c
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ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
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@ -0,0 +1,87 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootstate.h>
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#include <console/console.h>
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#include <fw_config.h>
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#include <gpio.h>
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static const struct pad_config dmic_enable_pads[] = {
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PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), /* DMIC_CLK0_R */
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PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), /* DMIC_DATA0_R */
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PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), /* DMIC_CLK1_R */
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PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), /* DMIC_DATA1_R */
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};
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static const struct pad_config dmic_disable_pads[] = {
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PAD_NC(GPP_R4, NONE),
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PAD_NC(GPP_R5, NONE),
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PAD_NC(GPP_R6, NONE),
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PAD_NC(GPP_R7, NONE),
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};
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static const struct pad_config i2s_enable_pads[] = {
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PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S_HP_SCLK_R */
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PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S_HP_SFRM_R */
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PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S_PCH_TX_HP_RX_STRAP */
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PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S_PCH_RX_HP_TX */
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PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), /* I2S_SPKR_SCLK_R */
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PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), /* I2S_SPKR_SFRM_R */
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PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), /* I2S_PCH_TX_SPKR_RX_R */
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PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4), /* I2S_PCH_RX_SPKR_TX */
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};
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static const struct pad_config i2s_disable_pads[] = {
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PAD_NC(GPP_R0, NONE),
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PAD_NC(GPP_R1, NONE),
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PAD_NC(GPP_R2, NONE),
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PAD_NC(GPP_R3, NONE),
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PAD_NC(GPP_S0, NONE),
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PAD_NC(GPP_S1, NONE),
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PAD_NC(GPP_S2, NONE),
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PAD_NC(GPP_S3, NONE),
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};
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static const struct pad_config bt_i2s_enable_pads[] = {
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PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), /* BT_I2S_BCLK */
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PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), /* BT_I2S_SYNC */
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PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), /* BT_I2S_SDO */
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PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), /* BT_I2S_SDI */
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PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), /* SSP2_SCLK */
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PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), /* SSP2_SFRM */
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PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), /* SSP_TXD */
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PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), /* SSP_RXD */
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};
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static const struct pad_config bt_i2s_disable_pads[] = {
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PAD_NC(GPP_VGPIO_30, NONE),
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PAD_NC(GPP_VGPIO_31, NONE),
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PAD_NC(GPP_VGPIO_32, NONE),
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PAD_NC(GPP_VGPIO_33, NONE),
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PAD_NC(GPP_VGPIO_34, NONE),
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PAD_NC(GPP_VGPIO_35, NONE),
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PAD_NC(GPP_VGPIO_36, NONE),
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PAD_NC(GPP_VGPIO_37, NONE),
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};
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static void fw_config_handle(void *unused)
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{
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if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) {
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printk(BIOS_INFO, "Disable audio related GPIO pins.\n");
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gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads));
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gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads));
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gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads));
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return;
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}
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if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_NAU88L25B_I2S))) {
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printk(BIOS_INFO, "Configure audio over I2S with MAX98360 NAU88L25B.\n");
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gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads));
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gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads));
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printk(BIOS_INFO, "BT offload enabled\n");
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gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads));
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} else {
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printk(BIOS_INFO, "BT offload disabled\n");
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gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads));
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}
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}
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BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
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@ -1,6 +1,352 @@
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chip soc/intel/alderlake
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fw_config
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field KB_BL 0 0
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device domain 0 on
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option KB_BL_ABSENT 0
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end
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option KB_BL_PRESENT 1
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end
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field KB_MT 1 1
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option KB_MT_CROS 0
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option KB_MT_RGB 1
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end
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field AUDIO 2 3
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option AUDIO_UNKNOWN 0
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option MAX98360_NAU88L25B_I2S 1
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end
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end
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chip soc/intel/alderlake
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register "sagv" = "SaGv_Enabled"
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register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_C1
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register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable M.2 WWAN
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register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable M.2 WWAN
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# FIVR configurations are disabled since the board doesn't have V1p05 and Vnn
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# bypass rails implemented.
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register "ext_fivr_settings" = "{
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.configure_ext_fivr = 1,
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}"
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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#| Field | Value |
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#+-------------------+---------------------------+
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#| I2C0 | Audio |
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#| I2C1 | cr50 TPM. Early init is |
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#| | required to set up a BAR |
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#| | for TPM communication |
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#| I2C5 | Trackpad |
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#+-------------------+---------------------------+
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register "common_soc_config" = "{
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 650,
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.fall_time_ns = 400,
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.data_hold_time_ns = 50,
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},
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.i2c[1] = {
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.early_init = 1,
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 600,
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.fall_time_ns = 400,
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.data_hold_time_ns = 50,
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},
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.i2c[5] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 650,
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.fall_time_ns = 400,
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.data_hold_time_ns = 50,
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},
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}"
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device domain 0 on
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device ref dtt on
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chip drivers/intel/dptf
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## sensor information
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register "options.tsr[0].desc" = ""DRAM""
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register "options.tsr[1].desc" = ""Soc""
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register "options.tsr[2].desc" = ""Charger""
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# TODO: below values are initial reference values only
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## Active Policy
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register "policies.active" = "{
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[0] = {
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.target = DPTF_CPU,
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.thresholds = {
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TEMP_PCT(85, 90),
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TEMP_PCT(75, 80),
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TEMP_PCT(68, 70),
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TEMP_PCT(62, 60),
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TEMP_PCT(55, 50),
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TEMP_PCT(50, 40),
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TEMP_PCT(40, 30),
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}
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},
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[1] = {
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.target = DPTF_TEMP_SENSOR_1,
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.thresholds = {
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TEMP_PCT(60, 90),
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TEMP_PCT(55, 80),
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TEMP_PCT(52, 70),
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TEMP_PCT(48, 60),
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TEMP_PCT(44, 50),
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TEMP_PCT(40, 40),
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TEMP_PCT(36, 30),
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}
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}
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}"
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## Passive Policy
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register "policies.passive" = "{
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[0] = DPTF_PASSIVE(CPU, CPU, 90, 5000),
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[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 55, 5000),
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[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 5000),
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[3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 55, 5000),
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}"
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## Critical Policy
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register "policies.critical" = "{
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[0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN),
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[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
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[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
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[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
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}"
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register "controls.power_limits" = "{
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.pl1 = {
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.min_power = 18000,
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.max_power = 20000,
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.time_window_min = 28 * MSECS_PER_SEC,
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.time_window_max = 32 * MSECS_PER_SEC,
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.granularity = 200,
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},
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.pl2 = {
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.min_power = 43000,
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.max_power = 43000,
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.time_window_min = 28 * MSECS_PER_SEC,
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.time_window_max = 32 * MSECS_PER_SEC,
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.granularity = 1000,
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}
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}"
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## Charger Performance Control (Control, mA)
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register "controls.charger_perf" = "{
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[0] = { 255, 1700 },
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[1] = { 24, 1500 },
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[2] = { 16, 1000 },
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[3] = { 8, 500 }
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}"
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## Fan Performance Control (Percent, Speed, Noise, Power)
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register "controls.fan_perf" = "{
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[0] = { 90, 6700, 220, 2200, },
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[1] = { 80, 5800, 180, 1800, },
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[2] = { 70, 5000, 145, 1450, },
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[3] = { 60, 4900, 115, 1150, },
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[4] = { 50, 3838, 90, 900, },
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[5] = { 40, 2904, 55, 550, },
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[6] = { 30, 2337, 30, 300, },
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[7] = { 20, 1608, 15, 150, },
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[8] = { 10, 800, 10, 100, },
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[9] = { 0, 0, 0, 50, }
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}"
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## Fan options
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register "options.fan.fine_grained_control" = "1"
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register "options.fan.step_size" = "2"
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device generic 0 alias dptf_policy on end
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end
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end
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device ref tbt_pcie_rp0 off end
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device ref tbt_pcie_rp1 off end
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device ref tbt_pcie_rp2 off end
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device ref tcss_dma0 off end
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device ref tcss_dma1 off end
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device ref pcie4_0 on
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# Enable CPU PCIE RP 1 using CLK 0
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register "cpu_pcie_rp[CPU_RP(1)]" = "{
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.clk_req = 0,
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.clk_src = 0,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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end
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device ref cnvi_wifi on
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chip drivers/wifi/generic
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register "wake" = "GPE0_PME_B0"
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device generic 0 on end
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end
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end
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device ref i2c0 on
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chip drivers/i2c/nau8825
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register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A23)"
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register "jkdet_enable" = "1"
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register "jkdet_pull_enable" = "0"
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register "jkdet_pull_up" = "0"
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register "jkdet_polarity" = "1" # ActiveLow
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register "vref_impedance" = "2" # 125kOhm
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register "micbias_voltage" = "6" # 2.754
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register "sar_threshold_num" = "4"
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register "sar_threshold[0]" = "0x0C"
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register "sar_threshold[1]" = "0x1C"
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register "sar_threshold[2]" = "0x38"
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register "sar_threshold[3]" = "0x60"
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register "sar_hysteresis" = "1"
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register "sar_voltage" = "6"
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register "sar_compare_time" = "0" # 500ns
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register "sar_sampling_time" = "0" # 2us
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register "short_key_debounce" = "2" # 100ms
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register "jack_insert_debounce" = "7" # 512ms
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register "jack_eject_debounce" = "7" # 512ms
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device i2c 1a on
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probe AUDIO MAX98360_NAU88L25B_I2S
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end
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end
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end #I2C0
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device ref i2c1 on
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chip drivers/i2c/tpm
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register "hid" = ""GOOG0005""
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register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
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device i2c 50 on end
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end
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end
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device ref i2c5 on
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chip drivers/i2c/generic
|
||||||
|
register "hid" = ""ELAN0000""
|
||||||
|
register "desc" = ""ELAN Touchpad""
|
||||||
|
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
|
||||||
|
register "wake" = "GPE0_DW2_14"
|
||||||
|
register "probed" = "1"
|
||||||
|
device i2c 15 on end
|
||||||
|
end
|
||||||
|
chip drivers/i2c/hid
|
||||||
|
register "generic.hid" = ""PNP0C50""
|
||||||
|
register "generic.desc" = ""Synaptics Touchpad""
|
||||||
|
register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
|
||||||
|
register "generic.wake" = "GPE0_DW2_14"
|
||||||
|
register "generic.probed" = "1"
|
||||||
|
register "hid_desc_reg_offset" = "0x20"
|
||||||
|
device i2c 0x2c on end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
device ref hda on
|
||||||
|
chip drivers/generic/max98357a
|
||||||
|
register "hid" = ""MX98360A""
|
||||||
|
register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
|
||||||
|
register "sdmode_delay" = "5"
|
||||||
|
device generic 0 on
|
||||||
|
probe AUDIO MAX98360_NAU88L25B_I2S
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
device ref pcie_rp6 off end # PCIE6 WWAN
|
||||||
|
device ref pcie_rp7 on
|
||||||
|
chip drivers/net
|
||||||
|
register "wake" = "GPE0_DW0_07"
|
||||||
|
register "led_feature" = "0xe0"
|
||||||
|
register "customized_led0" = "0x23f"
|
||||||
|
register "customized_led2" = "0x028"
|
||||||
|
register "enable_aspm_l1_2" = "1"
|
||||||
|
device pci 00.0 on end
|
||||||
|
end
|
||||||
|
# Enable PCIE 7 using clk 6
|
||||||
|
register "pch_pcie_rp[PCH_RP(7)]" = "{
|
||||||
|
.clk_src = 6,
|
||||||
|
.clk_req = 6,
|
||||||
|
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||||
|
}"
|
||||||
|
end # RTL8125 Ethernet NIC
|
||||||
|
device ref pcie_rp8 off end # PCIE8 SD card
|
||||||
|
device ref pcie_rp9 off end # PCIE9-12 SSD
|
||||||
|
device ref gspi1 off end
|
||||||
|
device ref pch_espi on
|
||||||
|
chip ec/google/chromeec
|
||||||
|
use conn0 as mux_conn[0]
|
||||||
|
use conn1 as mux_conn[1]
|
||||||
|
device pnp 0c09.0 on end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
device ref pmc hidden
|
||||||
|
chip drivers/intel/pmc_mux
|
||||||
|
device generic 0 on
|
||||||
|
chip drivers/intel/pmc_mux/conn
|
||||||
|
use usb2_port1 as usb2_port
|
||||||
|
use tcss_usb3_port1 as usb3_port
|
||||||
|
device generic 0 alias conn0 on end
|
||||||
|
end
|
||||||
|
chip drivers/intel/pmc_mux/conn
|
||||||
|
use usb2_port3 as usb2_port
|
||||||
|
use tcss_usb3_port3 as usb3_port
|
||||||
|
device generic 1 alias conn1 on end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
device ref tcss_xhci on
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
device ref tcss_root_hub on
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""USB3 Type-C Port C0 (MLB)""
|
||||||
|
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||||
|
register "use_custom_pld" = "true"
|
||||||
|
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
|
||||||
|
device ref tcss_usb3_port1 on end
|
||||||
|
end
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""USB3 Type-C Port C1 (MLB)""
|
||||||
|
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||||
|
register "use_custom_pld" = "true"
|
||||||
|
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
|
||||||
|
device ref tcss_usb3_port3 on end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
device ref xhci on
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
device ref xhci_root_hub on
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""USB2 Type-C Port C0 (MLB)""
|
||||||
|
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||||
|
register "use_custom_pld" = "true"
|
||||||
|
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
|
||||||
|
device ref usb2_port1 on end
|
||||||
|
end
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""USB2 Type-C Port C1 (MLB)""
|
||||||
|
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||||
|
register "use_custom_pld" = "true"
|
||||||
|
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
|
||||||
|
device ref usb2_port3 on end
|
||||||
|
end
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""USB2 Camera""
|
||||||
|
register "type" = "UPC_TYPE_INTERNAL"
|
||||||
|
device ref usb2_port6 on end
|
||||||
|
end
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""USB2 Type-A Port A0 (MLB)""
|
||||||
|
register "type" = "UPC_TYPE_A"
|
||||||
|
register "use_custom_pld" = "true"
|
||||||
|
register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(1, 2))"
|
||||||
|
device ref usb2_port9 on end
|
||||||
|
end
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""USB2 Bluetooth""
|
||||||
|
register "type" = "UPC_TYPE_INTERNAL"
|
||||||
|
register "reset_gpio" =
|
||||||
|
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
|
||||||
|
device ref usb2_port10 on end
|
||||||
|
end
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""USB3 Type-A Port A0 (MLB)""
|
||||||
|
register "type" = "UPC_TYPE_USB3_A"
|
||||||
|
register "use_custom_pld" = "true"
|
||||||
|
register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(1, 2))"
|
||||||
|
device ref usb3_port1 on end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
end
|
end
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,11 @@
|
||||||
|
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||||
|
|
||||||
|
#include <baseboard/variants.h>
|
||||||
|
#include <chip.h>
|
||||||
|
#include <fw_config.h>
|
||||||
|
|
||||||
|
void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
|
||||||
|
{
|
||||||
|
config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO,
|
||||||
|
MAX98360_NAU88L25B_I2S));
|
||||||
|
}
|
||||||
Loading…
Reference in New Issue