From 3051a9ecfa4796de3e60b22df808a61e20da3b43 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 17 Feb 2021 20:43:04 +0200 Subject: [PATCH] nb/intel/x4x: Use a variable for s3resume MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This helps towards unified chipset_power_state. Change-Id: I8f152dc9f1e0f26e4777489913e9fb2c9cd3dac0 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/50974 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/northbridge/intel/x4x/raminit.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 59abe4d1de..8ff0ffc19a 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -688,11 +688,14 @@ void sdram_initialize(int boot_path, const u8 *spd_map) printk(BIOS_DEBUG, "RAM initialization finished.\n"); - cbmem_was_inited = !cbmem_recovery(s.boot_path == BOOT_PATH_RESUME); + int s3resume = boot_path == BOOT_PATH_RESUME; + + cbmem_was_inited = !cbmem_recovery(s3resume); if (!fast_boot) mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, &s, sizeof(s)); - if (s.boot_path == BOOT_PATH_RESUME && !cbmem_was_inited) { + + if (s3resume && !cbmem_was_inited) { /* Failed S3 resume, reset to come up cleanly */ system_reset(); }