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soc/intel/bdw,nb/intel/hsw: correct mask for panel power cycle delay 

Correct the mask for the power cycle delay from 0xff to 0x1f, to
represent the actual maximum value according to Intel graphics PRM for
Haswell, Volume 2c and Intel graphics PRM for Broadwell, Volume 2c.

Change-Id: Ib187f1ca6474325475e5ae4cc1b2ffbce12f10bf
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48957
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michael Niewöhner 2020-12-28 15:00:39 +01:00
parent 4ea47c32b0
commit 3054a19279
2 changed files with 4 additions and 4 deletions
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4
src/northbridge/intel/haswell/gma.c
View File

@ -273,8 +273,8 @@ static void gma_setup_panel(struct device *dev)
/* Setup Panel Power Cycle Delay */
if (conf->gpu_panel_power_cycle_delay) {
reg32 = gtt_read(PCH_PP_DIVISOR);
reg32 &= ~0xff;
reg32 |= conf->gpu_panel_power_cycle_delay & 0xff;
reg32 &= ~0x1f;
reg32 |= conf->gpu_panel_power_cycle_delay & 0x1f;
gtt_write(PCH_PP_DIVISOR, reg32);
}

4
src/soc/intel/broadwell/gma.c
View File

@ -314,8 +314,8 @@ static void gma_setup_panel(struct device *dev)
/* Setup Panel Power Cycle Delay */
if (conf->gpu_panel_power_cycle_delay) {
reg32 = gtt_read(PCH_PP_DIVISOR);
reg32 &= ~0xff;
reg32 |= conf->gpu_panel_power_cycle_delay & 0xff;
reg32 &= ~0x1f;
reg32 |= conf->gpu_panel_power_cycle_delay & 0x1f;
gtt_write(PCH_PP_DIVISOR, reg32);
}