diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig
index 806a08ec6e..5df8002715 100644
--- a/src/cpu/intel/Kconfig
+++ b/src/cpu/intel/Kconfig
@@ -31,6 +31,7 @@ source src/cpu/intel/socket_FCBGA559/Kconfig
 source src/cpu/intel/socket_mFCBGA479/Kconfig
 source src/cpu/intel/socket_mFCPGA478/Kconfig
 source src/cpu/intel/socket_mPGA478/Kconfig
+source src/cpu/intel/socket_mPGA478MN/Kconfig
 source src/cpu/intel/socket_mPGA479M/Kconfig
 source src/cpu/intel/socket_mPGA603/Kconfig
 source src/cpu/intel/socket_mPGA604/Kconfig
diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc
index 536b40e565..1874075c37 100644
--- a/src/cpu/intel/Makefile.inc
+++ b/src/cpu/intel/Makefile.inc
@@ -13,6 +13,7 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_FCBGA559) += socket_FCBGA559
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCBGA479) += socket_mFCBGA479
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCPGA478) += socket_mFCPGA478
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA478) += socket_mPGA478
+subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA478MN) += socket_mPGA478MN
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA479M) += socket_mPGA479M
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA603) += socket_mPGA603
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604
diff --git a/src/cpu/intel/socket_mPGA478MN/Kconfig b/src/cpu/intel/socket_mPGA478MN/Kconfig
new file mode 100644
index 0000000000..7c4dbc5b29
--- /dev/null
+++ b/src/cpu/intel/socket_mPGA478MN/Kconfig
@@ -0,0 +1,18 @@
+config CPU_INTEL_SOCKET_MPGA478MN
+	bool
+	select CPU_INTEL_MODEL_1067X
+	select CPU_INTEL_MODEL_6FX
+	select MMX
+	select SSE
+
+if CPU_INTEL_SOCKET_MPGA478MN
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xffaf8000
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x8000
+
+endif
diff --git a/src/cpu/intel/socket_mPGA478MN/Makefile.inc b/src/cpu/intel/socket_mPGA478MN/Makefile.inc
new file mode 100644
index 0000000000..407861e164
--- /dev/null
+++ b/src/cpu/intel/socket_mPGA478MN/Makefile.inc
@@ -0,0 +1,14 @@
+subdirs-y += ../model_6fx
+subdirs-y += ../model_1067x
+subdirs-y += ../../x86/tsc
+subdirs-y += ../../x86/mtrr
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/smm
+subdirs-y += ../microcode
+subdirs-y += ../hyperthreading
+subdirs-y += ../speedstep
+
+# Use Intel Core (not Core 2) code for CAR init, any CPU might be used.
+cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
+romstage-y += ../car/romstage.c