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mb/intel/mtlrvp: Add chip configuration for I2C devices 

This patch adds below chip configuration for I2C devices for mtlrvp.

+-----------+--------------------+-------------+
| INTERFACE | PCI Number (B:D:F) | DEVICE      |
+-----------+--------------------+-------------+
|   I2C0    | 0:0x15:0           | CAM1        |
+-----------+--------------------+-------------+
|   I2C1    | 0:0x15:1           | CAM0        |
+-----------+--------------------+-------------+
|   I2C2    | 0:0x15:2           | NC          |
+-----------+--------------------+-------------+
|   I2C3    | 0:0x15:3           | HID         |
+-----------+--------------------+-------------+
|   I2C4    | 0:0x15:4           | NC          |
+-----------+--------------------+-------------+
|   I2C5    | 0:0x15:5           | NC          |
+-----------+--------------------+-------------+

BUG=b:224325352
BRANCH=None
TEST=Able to boot mtlrvp (LP5/DDR5) to ChromeOS. Also verify serial bus
enumeration through lspci.

00:15.0 Serial bus controller: Intel Corporation Device 7e78 (rev 01)
00:15.1 Serial bus controller: Intel Corporation Device 7e79 (rev 01)
00:15.3 Serial bus controller: Intel Corporation Device 7e7b (rev 01)

Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: Ia5964472be902041f961187c0072a89055badd4f
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
This commit is contained in:
Harsha B R 2023-01-31 18:49:32 +05:30 committed by Sridhar Siricilla
parent 9c471e7def
commit 306bd40939
1 changed files with 23 additions and 0 deletions
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23
src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
View File

@ -46,6 +46,29 @@ chip soc/intel/meteorlake
[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
}"
register "serial_io_i2c_mode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci,
[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
[PchSerialIoIndexI2C3] = PchSerialIoPci,
[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
}"
# Intel Common SoC Config
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[0] = {
.speed = I2C_SPEED_FAST,
},
.i2c[1] = {
.speed = I2C_SPEED_FAST,
},
.i2c[3] = {
.speed = I2C_SPEED_FAST,
},
}"
device domain 0 on
device ref igpu on end
device ref heci1 on end