sb,soc/intel: Address TCO SECOND_TO_STS name collision

Later soc/intel/common/smbus addresses TCO2_STS as a separate
16-bit register, while baytrail and braswell assumes 32-bit
wide TCO1_STS to extend as TCO2_STS.

In src/soc/intel/denverton_ns:
  #define TCO2_STS_SECOND_TO 0x02

In soc/intel/baytrail,braswell:
  #define SECOND_TO_STS (1 << 17)

Elsewehere
  #define SECOND_TO_STS (1 << 1)

It's expected that we remove the first (1 << 17) case and only
access TCO2_STS as a separate 16-bit register. For now, use
unique names to avoid confusion.

Change-Id: I07cc46a9d600b2bf2f23588b26891268e9ce4de0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>

src/soc/intel/alderlake/elog.c

@@ -170,7 +170,7 @@ static void pch_log_power_and_resets(const struct chipset_power_state *ps)
 
 	/* TCO Timeout */
 	if (ps->prev_sleep_state != ACPI_S3 &&
-	    ps->tco2_sts & TCO_STS_SECOND_TO)
+	    ps->tco2_sts & TCO2_STS_SECOND_TO)
 		elog_add_event(ELOG_TYPE_TCO_RESET);
 
 	/* Power Button Override */

src/soc/intel/apollolake/include/soc/smbus.h

@@ -7,7 +7,7 @@
 #define TCO1_STS			0x04
 #define  TCO_TIMEOUT			(1 << 3)
 #define TCO2_STS			0x06
-#define  TCO_STS_SECOND_TO		(1 << 1)
+#define  TCO2_STS_SECOND_TO		(1 << 1)
 #define  TCO_INTRD_DET			(1 << 0)
 #define TCO1_CNT			0x08
 #define  TCO_LOCK			(1 << 12)

src/soc/intel/baytrail/elog.c

@@ -22,7 +22,7 @@ static void log_power_and_resets(const struct chipset_power_state *ps)
 	if (ps->gen_pmcon1 & RPS)
 		elog_add_event(ELOG_TYPE_RTC_RESET);
 
-	if (ps->tco_sts & SECOND_TO_STS)
+	if (ps->tco_sts & TCO1_32_STS_SECOND_TO_STS)
 		elog_add_event(ELOG_TYPE_TCO_RESET);
 
 	if (ps->pm1_sts & PRBTNOR_STS)

src/soc/intel/baytrail/include/soc/pm.h

@@ -226,7 +226,7 @@
 #if CONFIG(TCO_SPACE_NOT_YET_SPLIT)
 #define TCO_RLD			0x60
 #define TCO_STS			0x64
-#	define SECOND_TO_STS	(1 << 17)
+#	define TCO1_32_STS_SECOND_TO_STS	(1 << 17)
 #	define TCO_TIMEOUT	(1 << 3)
 #define TCO1_CNT		0x68
 #	define TCO_LOCK		(1 << 12)

src/soc/intel/braswell/elog.c

@@ -22,7 +22,7 @@ static void log_power_and_resets(const struct chipset_power_state *ps)
 	if (ps->gen_pmcon1 & RPS)
 		elog_add_event(ELOG_TYPE_RTC_RESET);
 
-	if (ps->tco_sts & SECOND_TO_STS)
+	if (ps->tco_sts & TCO1_32_STS_SECOND_TO_STS)
 		elog_add_event(ELOG_TYPE_TCO_RESET);
 
 	if (ps->pm1_sts & PRBTNOR_STS)

src/soc/intel/braswell/include/soc/pm.h

@@ -188,7 +188,7 @@
 #if CONFIG(TCO_SPACE_NOT_YET_SPLIT)
 #define TCO_RLD			0x60
 #define TCO_STS			0x64
-#	define SECOND_TO_STS	(1 << 17)
+#	define TCO1_32_STS_SECOND_TO_STS	(1 << 17)
 #	define TCO_TIMEOUT	(1 << 3)
 #define TCO1_CNT		0x68
 #	define TCO_LOCK		(1 << 12)

src/soc/intel/cannonlake/elog.c

@@ -135,7 +135,7 @@ static void pch_log_power_and_resets(const struct chipset_power_state *ps)
 
 	/* TCO Timeout */
 	if (ps->prev_sleep_state != ACPI_S3 &&
-	    ps->tco2_sts & TCO_STS_SECOND_TO)
+	    ps->tco2_sts & TCO2_STS_SECOND_TO)
 		elog_add_event(ELOG_TYPE_TCO_RESET);
 
 	/* Power Button Override */

src/soc/intel/common/block/smbus/tco.c

@@ -72,7 +72,7 @@ uint32_t tco_reset_status(void)
 
 	/* TCO Status 2 register */
 	tco2_sts = tco_read_reg(TCO2_STS);
-	tco_write_reg(TCO2_STS, tco2_sts | TCO_STS_SECOND_TO);
+	tco_write_reg(TCO2_STS, tco2_sts | TCO2_STS_SECOND_TO);
 
 	return (tco2_sts << 16) | tco1_sts;
 }

src/soc/intel/common/pch/include/intelpch/smbus.h

@@ -7,7 +7,7 @@
 #define TCO1_STS			0x04
 #define  TCO_TIMEOUT			(1 << 3)
 #define TCO2_STS			0x06
-#define  TCO_STS_SECOND_TO		(1 << 1)
+#define  TCO2_STS_SECOND_TO		(1 << 1)
 #define  TCO_INTRD_DET			(1 << 0)
 #define TCO1_CNT			0x08
 #define  TCO_LOCK			(1 << 12)

src/soc/intel/icelake/elog.c

@@ -70,7 +70,7 @@ static void pch_log_power_and_resets(const struct chipset_power_state *ps)
 
 	/* TCO Timeout */
 	if (ps->prev_sleep_state != ACPI_S3 &&
-	    ps->tco2_sts & TCO_STS_SECOND_TO)
+	    ps->tco2_sts & TCO2_STS_SECOND_TO)
 		elog_add_event(ELOG_TYPE_TCO_RESET);
 
 	/* Power Button Override */

src/soc/intel/jasperlake/elog.c

@@ -143,7 +143,7 @@ static void pch_log_power_and_resets(const struct chipset_power_state *ps)
 
 	/* TCO Timeout */
 	if (ps->prev_sleep_state != ACPI_S3 &&
-	    ps->tco2_sts & TCO_STS_SECOND_TO)
+	    ps->tco2_sts & TCO2_STS_SECOND_TO)
 		elog_add_event(ELOG_TYPE_TCO_RESET);
 
 	/* Power Button Override */

src/soc/intel/meteorlake/elog.c

@@ -173,7 +173,7 @@ static void pch_log_power_and_resets(const struct chipset_power_state *ps)
 
 	/* TCO Timeout */
 	if (ps->prev_sleep_state != ACPI_S3 &&
-	    ps->tco2_sts & TCO_STS_SECOND_TO)
+	    ps->tco2_sts & TCO2_STS_SECOND_TO)
 		elog_add_event(ELOG_TYPE_TCO_RESET);
 
 	/* Power Button Override */

src/soc/intel/skylake/elog.c

@@ -202,7 +202,7 @@ static void pch_log_power_and_resets(const struct chipset_power_state *ps)
 
 	/* TCO Timeout */
 	if (ps->prev_sleep_state != ACPI_S3 &&
-	    ps->tco2_sts & TCO_STS_SECOND_TO)
+	    ps->tco2_sts & TCO2_STS_SECOND_TO)
 		elog_add_event(ELOG_TYPE_TCO_RESET);
 
 	/* Power Button Override */

src/soc/intel/tigerlake/elog.c

@@ -178,7 +178,7 @@ static void pch_log_power_and_resets(const struct chipset_power_state *ps)
 
 	/* TCO Timeout */
 	if (ps->prev_sleep_state != ACPI_S3 &&
-	    ps->tco2_sts & TCO_STS_SECOND_TO)
+	    ps->tco2_sts & TCO2_STS_SECOND_TO)
 		elog_add_event(ELOG_TYPE_TCO_RESET);
 
 	/* Power Button Override */

src/soc/intel/xeon_sp/include/soc/smbus.h

@@ -7,7 +7,7 @@
 #define TCO1_STS			0x04
 #define  TCO_TIMEOUT			(1 << 3)
 #define TCO2_STS			0x06
-#define  TCO_STS_SECOND_TO		(1 << 1)
+#define  TCO2_STS_SECOND_TO		(1 << 1)
 #define  TCO_INTRD_DET			(1 << 0)
 #define TCO1_CNT			0x08
 #define  TCO_LOCK			(1 << 12)

src/southbridge/intel/bd82x6x/pch.h

@@ -469,7 +469,7 @@ void early_usb_init(const struct southbridge_usb_port *portmap);
 #define   TCO1_TIMEOUT	(1 << 3)
 #define   DMISCI_STS	(1 << 9)
 #define TCO2_STS	0x66
-#define   SECOND_TO_STS	(1 << 1)
+#define   TCO2_STS_SECOND_TO	(1 << 1)
 #define TCO1_CNT	0x68
 #define   TCO_TMR_HLT	(1 << 11)
 #define   TCO_LOCK	(1 << 12)

src/southbridge/intel/common/tco.h

@@ -15,7 +15,7 @@
 #define TCO1_STS		0x04
 #define  TCO1_TIMEOUT		(1 << 3)
 #define TCO2_STS		0x06
-#define  SECOND_TO_STS		(1 << 1)
+#define  TCO2_STS_SECOND_TO	(1 << 1)
 #define TCO1_CNT		0x08
 #define  TCO_TMR_HLT		(1 << 11)
 

src/southbridge/intel/common/watchdog.c

@@ -33,7 +33,7 @@ void watchdog_off(void)
 
 	/* Clear TCO timeout status. */
 	write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO1_TIMEOUT);
-	write_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS, SECOND_TO_STS);
+	write_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS, TCO2_STS_SECOND_TO);
 
 	printk(BIOS_DEBUG, "ICH-NM10-PCH: watchdog disabled\n");
 }

src/southbridge/intel/lynxpoint/elog.c

@@ -124,7 +124,7 @@ void pch_log_state(void)
 		elog_add_event(ELOG_TYPE_PWROK_FAIL);
 
 	/* Second TCO Timeout */
-	if (tco2_sts & SECOND_TO_STS)
+	if (tco2_sts & TCO2_STS_SECOND_TO)
 		elog_add_event(ELOG_TYPE_TCO_RESET);
 
 	/* Power Button Override */

src/southbridge/intel/lynxpoint/pch.h

@@ -623,7 +623,7 @@ void mainboard_config_rcba(void);
 #define TCO1_STS	0x64
 #define   DMISCI_STS	(1 << 9)
 #define TCO2_STS	0x66
-#define   SECOND_TO_STS	(1 << 1)
+#define   TCO2_STS_SECOND_TO	(1 << 1)
 #endif
 
 #define ALT_GP_SMI_EN2	0x5c