nb/intel/sandybridge: Use proper names to refer to training steps
Now that the purpose of each training algorithm is clear, replace the last instances of the original names in comments and print statements with the current, correct names. Also, print which channel has failed command training, for completeness and consistency with other errors. Change-Id: I9cc5c4b04499297825ca004c6bd1648a68449d2c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48601 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -1231,7 +1231,7 @@ static int find_roundtrip_latency(ramctr_timing *ctrl, int channel, int slotrank
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if (!some_works) {
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/* Guard against roundtrip latency underflow */
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if (ctrl->timings[channel][slotrank].roundtrip_latency < 2) {
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printk(BIOS_EMERG, "402x discovery failed (1): %d, %d\n",
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printk(BIOS_EMERG, "Roundtrip latency underflow: %d, %d\n",
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channel, slotrank);
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return MAKE_ERR;
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}
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@ -1250,7 +1250,7 @@ static int find_roundtrip_latency(ramctr_timing *ctrl, int channel, int slotrank
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/* Guard against I/O latency overflow */
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if (ctrl->timings[channel][slotrank].io_latency >= 0x10) {
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printk(BIOS_EMERG, "402x discovery failed (2): %d, %d\n",
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printk(BIOS_EMERG, "I/O latency overflow: %d, %d\n",
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channel, slotrank);
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return MAKE_ERR;
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}
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@ -1499,7 +1499,7 @@ static int tx_dq_write_leveling(ramctr_timing *ctrl, int channel, int slotrank)
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struct run rn = get_longest_zero_run(stats[lane], ARRAY_SIZE(stats[lane]));
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if (rn.all || rn.length < 8) {
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printk(BIOS_EMERG, "tx_dq discovery failed: %d, %d, %d\n",
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printk(BIOS_EMERG, "tx_dq write leveling failed: %d, %d, %d\n",
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channel, slotrank, lane);
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/*
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* With command training not being done yet, the lane can be erroneous.
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@ -1634,7 +1634,7 @@ static int write_level_rank(ramctr_timing *ctrl, int channel, int slotrank)
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ctrl->timings[channel][slotrank].lanes[lane].tx_dqs = rn.start;
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if (rn.all) {
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printk(BIOS_EMERG, "tx_dqs discovery failed: %d, %d, %d\n",
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printk(BIOS_EMERG, "JEDEC write leveling failed: %d, %d, %d\n",
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channel, slotrank, lane);
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return MAKE_ERR;
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@ -2102,7 +2102,7 @@ int command_training(ramctr_timing *ctrl)
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/*
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* Dual DIMM per channel:
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* Issue:
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* While c320c discovery seems to succeed raminit will fail in write training.
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* While command training seems to succeed, raminit will fail in write training.
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*
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* Workaround:
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* Skip 1T in dual DIMM mode, that's only supported by a few DIMMs.
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@ -2124,7 +2124,7 @@ int command_training(ramctr_timing *ctrl)
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}
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if (err) {
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printk(BIOS_EMERG, "c320c discovery failed\n");
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printk(BIOS_EMERG, "Command training failed: %d\n", channel);
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return err;
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}
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@ -2176,7 +2176,7 @@ static int find_read_mpr_margin(ramctr_timing *ctrl, int channel, int slotrank,
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edges[lane] = rn.middle;
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if (rn.all) {
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printk(BIOS_EMERG, "edge discovery failed: %d, %d, %d\n", channel,
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printk(BIOS_EMERG, "Read MPR training failed: %d, %d, %d\n", channel,
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slotrank, lane);
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return MAKE_ERR;
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}
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@ -2376,7 +2376,7 @@ static int find_agrsv_read_margin(ramctr_timing *ctrl, int channel, int slotrank
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edges[lane] = (lower[lane] + upper[lane]) / 2;
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if (rn.all || (lower[lane] > upper[lane])) {
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printk(BIOS_EMERG, "edge write discovery failed: "
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printk(BIOS_EMERG, "Aggressive read training failed: "
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"%d, %d, %d\n", channel, slotrank, lane);
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return MAKE_ERR;
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@ -2482,7 +2482,7 @@ int aggressive_write_training(ramctr_timing *ctrl)
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if (enable_iosav_opt)
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MCHBAR32(MCMNTS_SPARE) = 1;
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printram("discover tx_dq write:\n");
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printram("Aggresive write training:\n");
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for (i = 0; i < ARRAY_SIZE(wr_vref_offsets); i++) {
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FOR_ALL_POPULATED_CHANNELS {
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@ -2520,8 +2520,8 @@ int aggressive_write_training(ramctr_timing *ctrl)
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rn = get_longest_zero_run(stats, MAX_TX_DQ + 1);
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if (rn.all) {
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printk(BIOS_EMERG,
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"tx_dq write discovery failed: "
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printk(BIOS_EMERG, "Aggressive "
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"write training failed: "
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"%d, %d, %d\n", channel,
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slotrank, lane);
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