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Drop CONFIG_CHIP_NAME. Those config statements in Config.lb should 

be used unconditionally, and the names don't hurt.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4042 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2009-04-01 13:43:21 +00:00 committed by Stefan Reinauer
parent 77cf00850f
commit 3081bdfa44
126 changed files with 45 additions and 381 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/config/Options.lb
View File

@ -854,12 +854,6 @@ end
# Misc options
###############################################
define CONFIG_CHIP_NAME
default 0
export always
comment "Compile in the chip name"
end
define CONFIG_GDB_STUB
default 0
export used

5
src/cpu/amd/socket_754/Config.lb
View File

@ -1,7 +1,4 @@
uses CONFIG_CHIP_NAME
if CONFIG_CHIP_NAME
config chip.h
end
config chip.h
object socket_754.o
dir /cpu/amd/model_fxx

6
src/cpu/amd/socket_939/Config.lb
View File

@ -1,8 +1,4 @@
uses CONFIG_CHIP_NAME
if CONFIG_CHIP_NAME
config chip.h
end
config chip.h
object socket_939.o

6
src/cpu/amd/socket_940/Config.lb
View File

@ -1,8 +1,4 @@
uses CONFIG_CHIP_NAME
if CONFIG_CHIP_NAME
config chip.h
end
config chip.h
object socket_940.o

5
src/cpu/amd/socket_AM2/Config.lb
View File

@ -1,12 +1,9 @@
uses CONFIG_CHIP_NAME
uses K8_REV_F_SUPPORT
uses K8_HT_FREQ_1G_SUPPORT
uses DIMM_SUPPORT
uses CPU_SOCKET_TYPE
if CONFIG_CHIP_NAME
config chip.h
end
config chip.h
default K8_REV_F_SUPPORT=1
#Opteron K8 1G HT Support

5
src/cpu/amd/socket_F/Config.lb
View File

@ -1,12 +1,9 @@
uses CONFIG_CHIP_NAME
uses K8_REV_F_SUPPORT
uses K8_HT_FREQ_1G_SUPPORT
uses DIMM_SUPPORT
uses CPU_SOCKET_TYPE
if CONFIG_CHIP_NAME
config chip.h
end
config chip.h
default K8_REV_F_SUPPORT=1
#Opteron K8 1G HT Support

5
src/cpu/amd/socket_F_1207/Config.lb
View File

@ -17,7 +17,6 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
uses CONFIG_CHIP_NAME
uses PCI_IO_CFG_EXT
uses MMCONF_SUPPORT
uses HT3_SUPPORT
@ -30,9 +29,7 @@ uses CDB
uses PCI_BUS_SEGN_BITS
uses CAR_FAM10
if CONFIG_CHIP_NAME
config chip.h
end
config chip.h
default PCI_IO_CFG_EXT=1

5
src/cpu/amd/socket_S1G1/Config.lb
View File

@ -1,12 +1,9 @@
uses CONFIG_CHIP_NAME
uses K8_REV_F_SUPPORT
uses K8_HT_FREQ_1G_SUPPORT
uses DIMM_SUPPORT
uses CPU_SOCKET_TYPE
if CONFIG_CHIP_NAME
config chip.h
end
config chip.h
default K8_REV_F_SUPPORT=1
#Opteron K8 1G HT Support

5
src/cpu/intel/socket_mPGA604_533Mhz/Config.lb
View File

@ -1,6 +1,3 @@
uses CONFIG_CHIP_NAME
if CONFIG_CHIP_NAME
config chip.h
end
config chip.h
object socket_mPGA604_533Mhz.o
dir /cpu/intel/model_f2x

5
src/drivers/generic/debug/debug_dev.c
View File

@ -231,13 +231,11 @@ static void print_tsc(void) {
static void debug_init(device_t dev)
{
#if CONFIG_CHIP_NAME
device_t parent;
#endif
if (!dev->enabled)
return;
switch(dev->path.pnp.device) {
#if CONFIG_CHIP_NAME
case 0:
parent = dev->bus->dev;
printk_debug("DEBUG: %s", dev_path(parent));
@ -247,7 +245,6 @@ static void debug_init(device_t dev)
printk_debug("\n");
}
break;
#endif
case 1:
print_pci_regs_all();

2
src/drivers/pci/onboard/onboard.c
View File

@ -73,8 +73,6 @@ static void onboard_enable(device_t dev)
}
struct chip_operations drivers_pci_onboard_ops = {
#if CONFIG_CHIP_NAME == 1
CHIP_NAME("Onboard PCI")
#endif
.enable_dev = onboard_enable,
};

6
src/include/device/device.h
View File

@ -15,16 +15,10 @@ struct smbus_bus_operations;
/* Chip operations */
struct chip_operations {
void (*enable_dev)(struct device *dev);
#if CONFIG_CHIP_NAME == 1
char *name;
#endif
};
#if CONFIG_CHIP_NAME == 1
#define CHIP_NAME(X) .name = X,
#else
#define CHIP_NAME(X)
#endif
struct bus;

4
src/mainboard/amd/dbm690t/Config.lb
View File

@ -178,9 +178,7 @@ end
##
## Include the secondary Configuration files
##
if CONFIG_CHIP_NAME
config chip.h
end
config chip.h
#The variables belong to mainboard are defined here.

4
src/mainboard/amd/dbm690t/Options.lb
View File

@ -73,7 +73,6 @@ uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
@ -157,9 +156,6 @@ default CONFIG_MAX_CPUS=2
default CONFIG_MAX_PHYSICAL_CPUS=1
default CONFIG_LOGICAL_CPUS=1
#CHIP_NAME ?
default CONFIG_CHIP_NAME=1
#1G memory hole
default HW_MEM_HOLE_SIZEK=0x100000

3
src/mainboard/amd/dbm690t/mainboard.c
View File

@ -263,9 +263,6 @@ int add_mainboard_resources(struct lb_memory *mem)
#endif
}
/*
* CONFIG_CHIP_NAME defined in Option.lb.
*/
struct chip_operations mainboard_ops = {
CHIP_NAME("AMD DBM690T Mainboard")
.enable_dev = dbm690t_enable,

4
src/mainboard/amd/pistachio/Config.lb
View File

@ -178,9 +178,7 @@ end
##
## Include the secondary Configuration files
##
if CONFIG_CHIP_NAME
config chip.h
end
config chip.h
#The variables belong to mainboard are defined here.

4
src/mainboard/amd/pistachio/Options.lb
View File

@ -73,7 +73,6 @@ uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
@ -157,9 +156,6 @@ default CONFIG_MAX_CPUS=2
default CONFIG_MAX_PHYSICAL_CPUS=1
default CONFIG_LOGICAL_CPUS=1
#CHIP_NAME ?
default CONFIG_CHIP_NAME=1
#1G memory hole
default HW_MEM_HOLE_SIZEK=0x100000

3
src/mainboard/amd/pistachio/mainboard.c
View File

@ -335,9 +335,6 @@ int add_mainboard_resources(struct lb_memory *mem)
#endif
}
/*
* CONFIG_CHIP_NAME defined in Option.lb.
*/
struct chip_operations mainboard_ops = {
CHIP_NAME("AMD Pistachio Mainboard")
.enable_dev = pistachio_enable,

4
src/mainboard/amd/serengeti_cheetah/Config.lb
View File

@ -253,9 +253,7 @@ end
##
## Include the secondary Configuration files
##
if CONFIG_CHIP_NAME
config chip.h
end
config chip.h
# sample config for amd/serengeti_cheetah
chip northbridge/amd/amdk8/root_complex

4
src/mainboard/amd/serengeti_cheetah/Options.lb
View File

@ -57,7 +57,6 @@ uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
@ -171,9 +170,6 @@ default ENABLE_APIC_EXT_ID=0
default APIC_ID_OFFSET=0x8
default LIFT_BSP_APIC_ID=1
#CHIP_NAME ?
default CONFIG_CHIP_NAME=1
#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
#2G
#default HW_MEM_HOLE_SIZEK=0x200000

2
src/mainboard/amd/serengeti_cheetah/mainboard.c
View File

@ -1,9 +1,7 @@
#include <device/device.h>
#include "chip.h"
#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("AMD Serengeti Cheetah Mainboard")
};
#endif

4
src/mainboard/amd/serengeti_cheetah_fam10/Config.lb
View File

@ -263,9 +263,7 @@ end
##
## Include the secondary Configuration files
##
if CONFIG_CHIP_NAME
config chip.h
end
config chip.h
dir /southbridge/amd/amd8151

4
src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
View File

@ -76,7 +76,6 @@ uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
@ -197,9 +196,6 @@ default ENABLE_APIC_EXT_ID=1
default APIC_ID_OFFSET=0x00
default LIFT_BSP_APIC_ID=1
#CHIP_NAME ?
default CONFIG_CHIP_NAME=1
#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
#2G
#default HW_MEM_HOLE_SIZEK=0x200000

2
src/mainboard/amd/serengeti_cheetah_fam10/mainboard.c
View File

@ -25,8 +25,6 @@
#include <device/pci_ops.h>
#include "chip.h"
#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("AMD family 10 Cheetah mainboard")
};
#endif

4
src/mainboard/asus/a8n_e/Config.lb
View File

@ -146,9 +146,7 @@ if USE_DCACHE_RAM
mainboardinit ./auto.inc
end
end
if CONFIG_CHIP_NAME
config chip.h
end
config chip.h
chip northbridge/amd/amdk8/root_complex # Root complex
device apic_cluster 0 on # APIC cluster

1
src/mainboard/asus/a8n_e/Options.lb
View File

@ -77,7 +77,6 @@ uses CONFIG_CONSOLE_SERIAL8250
uses CONFIG_CONSOLE_BTEXT
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK

2
src/mainboard/asus/a8n_e/mainboard.c
View File

@ -22,8 +22,6 @@
#include <device/device.h>
#include "chip.h"
#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("ASUS A8N-E Mainboard")
};
#endif

4
src/mainboard/asus/a8v-e_se/Config.lb
View File

@ -112,9 +112,7 @@ if USE_DCACHE_RAM
end
end
if CONFIG_CHIP_NAME
config chip.h
end
config chip.h
chip northbridge/amd/amdk8/root_complex # Root complex
device apic_cluster 0 on # APIC cluster

2
src/mainboard/asus/a8v-e_se/Options.lb
View File

@ -71,7 +71,6 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
# bx_b001- uses K8_HW_MEM_HOLE_SIZEK
@ -111,7 +110,6 @@ default CONFIG_MAX_CPUS = 2
default CONFIG_MAX_PHYSICAL_CPUS = 1
default CONFIG_LOGICAL_CPUS = 1
default HAVE_ACPI_TABLES = 1
# default CONFIG_CHIP_NAME = 1
# 1G memory hole
# bx_b001- default K8_HW_MEM_HOLE_SIZEK = 0x100000

2
src/mainboard/asus/a8v-e_se/mainboard.c
View File

@ -23,8 +23,6 @@
#include <device/pci_ids.h>
#include "chip.h"
#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("ASUS A8V-E SE Mainboard")
};
#endif

4
src/mainboard/asus/m2v-mx_se/Config.lb
View File

@ -115,9 +115,7 @@ if USE_DCACHE_RAM
end
end
if CONFIG_CHIP_NAME
config chip.h
end
config chip.h
chip northbridge/amd/amdk8/root_complex # Root complex
device apic_cluster 0 on # APIC cluster

3
src/mainboard/asus/m2v-mx_se/Options.lb
View File

@ -74,7 +74,6 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
# bx_b001- uses K8_HW_MEM_HOLE_SIZEK
@ -118,8 +117,6 @@ default HAVE_MAINBOARD_RESOURCES = 1
default HAVE_HIGH_TABLES = 1
default HAVE_LOW_TABLES = 0
# default CONFIG_CHIP_NAME = 1
# 1G memory hole
# bx_b001- default K8_HW_MEM_HOLE_SIZEK = 0x100000

2
src/mainboard/asus/m2v-mx_se/mainboard.c
View File

@ -37,8 +37,6 @@ int add_mainboard_resources(struct lb_memory *mem)
return 0;
}
#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("ASUS M2V-MX SE Mainboard")
};
#endif

2
src/mainboard/bcom/winnetp680/Options.lb
View File

@ -64,7 +64,6 @@ uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses CONFIG_PCI_ROM_RUN
uses CONFIG_CONSOLE_VGA
uses CONFIG_MAX_PCI_BUSES
uses CONFIG_CHIP_NAME
uses CONFIG_VIDEO_MB
uses CONFIG_IOAPIC
@ -74,7 +73,6 @@ default CONFIG_VIDEO_MB = 32
default CONFIG_CONSOLE_SERIAL8250 = 1
default CONFIG_PCI_ROM_RUN = 0
default CONFIG_CONSOLE_VGA = 0
default CONFIG_CHIP_NAME = 1
default HAVE_FALLBACK_BOOT = 1
default HAVE_MP_TABLE = 0
default CONFIG_UDELAY_TSC = 1

4
src/mainboard/broadcom/blast/Config.lb
View File

@ -145,9 +145,7 @@ end
##
## Include the secondary Configuration files
##
if CONFIG_CHIP_NAME
config chip.h
end
config chip.h
# sample config for broadcom/blast
chip northbridge/amd/amdk8/root_complex

4
src/mainboard/broadcom/blast/Options.lb
View File

@ -53,7 +53,6 @@ uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
@ -128,9 +127,6 @@ default CONFIG_MAX_CPUS=4
default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=1
#CHIP_NAME ?
default CONFIG_CHIP_NAME=1
#1G memory hole
default HW_MEM_HOLE_SIZEK=0x100000

2
src/mainboard/broadcom/blast/mainboard.c
View File

@ -1,9 +1,7 @@
#include <device/device.h>
#include "chip.h"
#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("Broadcom Blast Mainboard")
};
#endif

4
src/mainboard/gigabyte/ga_2761gxdk/Config.lb
View File

@ -223,9 +223,7 @@ end
##
## Include the secondary Configuration files
##
if CONFIG_CHIP_NAME
config chip.h
end
config chip.h
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on

4
src/mainboard/gigabyte/ga_2761gxdk/Options.lb
View File

@ -81,7 +81,6 @@ uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_USBDEBUG_DIRECT
uses CONFIG_PCI_ROM_RUN
@ -195,9 +194,6 @@ default ENABLE_APIC_EXT_ID=0
default APIC_ID_OFFSET=0x10
default LIFT_BSP_APIC_ID=1
#CHIP_NAME ?
default CONFIG_CHIP_NAME=1
#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
#2G
#default HW_MEM_HOLE_SIZEK=0x200000

2
src/mainboard/gigabyte/ga_2761gxdk/mainboard.c
View File

@ -26,8 +26,6 @@
#include <device/pci_ops.h>
#include "chip.h"
#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("GIGABYTE GA-2761GXDK Mainboard")
};
#endif

4
src/mainboard/gigabyte/m57sli/Config.lb
View File

@ -225,9 +225,7 @@ end
##
## Include the secondary Configuration files
##
if CONFIG_CHIP_NAME
config chip.h
end
config chip.h
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on

4
src/mainboard/gigabyte/m57sli/Options.lb
View File

@ -79,7 +79,6 @@ uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_USBDEBUG_DIRECT
uses CONFIG_PCI_ROM_RUN
@ -199,9 +198,6 @@ default ENABLE_APIC_EXT_ID=0
default APIC_ID_OFFSET=0x10
default LIFT_BSP_APIC_ID=1
#CHIP_NAME ?
default CONFIG_CHIP_NAME=1
#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
#2G
#default HW_MEM_HOLE_SIZEK=0x200000

2
src/mainboard/gigabyte/m57sli/mainboard.c
View File

@ -26,8 +26,6 @@
#include <device/pci_ops.h>
#include "chip.h"
#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("GIGABYTE GA-M57SLI Mainboard")
};
#endif

4
src/mainboard/intel/xe7501devkit/Config.lb
View File

@ -142,9 +142,7 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc
##
dir /pc80
if CONFIG_CHIP_NAME
config chip.h
end
config chip.h
# based on sample config for tyan/s2735
chip northbridge/intel/e7501

2
src/mainboard/intel/xe7501devkit/Options.lb
View File

@ -40,7 +40,6 @@ uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses DEBUG
@ -238,7 +237,6 @@ default CONFIG_IDE=1
default DEBUG=1
# default CPU_OPT="-g"
default CONFIG_CHIP_NAME=1
### End Options.lb
#

2
src/mainboard/intel/xe7501devkit/mainboard.c
View File

@ -1,9 +1,7 @@
#include <device/device.h>
#include "chip.h"
#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("Intel Xeon E7501 DevKit Mainboard")
};
#endif

4
src/mainboard/iwill/dk8_htx/Config.lb
View File

@ -261,9 +261,7 @@ end
##
## Include the secondary Configuration files
##
if CONFIG_CHIP_NAME
config chip.h
end
config chip.h
dir /southbridge/amd/amd8132

4
src/mainboard/iwill/dk8_htx/Options.lb
View File

@ -57,7 +57,6 @@ uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
@ -171,9 +170,6 @@ default ENABLE_APIC_EXT_ID=0
default APIC_ID_OFFSET=0x10
default LIFT_BSP_APIC_ID=1
#CHIP_NAME ?
default CONFIG_CHIP_NAME=1
#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
#2G
#default HW_MEM_HOLE_SIZEK=0x200000

3
src/mainboard/iwill/dk8_htx/mainboard.c
View File

@ -1,9 +1,6 @@
#include <device/device.h>
#include "chip.h"
#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("IWILL DK8-HTX Mainboard")
};
#endif

2
src/mainboard/jetway/j7f24/Options.lb
View File

@ -65,7 +65,6 @@ uses CONFIG_PCI_ROM_RUN
uses CONFIG_CONSOLE_VGA
uses CONFIG_MAX_PCI_BUSES
uses TTYS0_BAUD
uses CONFIG_CHIP_NAME
uses CONFIG_VIDEO_MB
uses CONFIG_IOAPIC
@ -75,7 +74,6 @@ default CONFIG_VIDEO_MB = 32
default CONFIG_CONSOLE_SERIAL8250 = 1
default CONFIG_PCI_ROM_RUN = 0
default CONFIG_CONSOLE_VGA = 0
default CONFIG_CHIP_NAME = 1
default HAVE_FALLBACK_BOOT = 1
default HAVE_MP_TABLE = 0
default CONFIG_UDELAY_TSC = 1

6
src/mainboard/kontron/986lcd-m/Options.lb
View File

@ -58,7 +58,6 @@ uses _RAMBASE
uses _ROMBASE
uses STACK_SIZE
uses HEAP_SIZE
uses CONFIG_CHIP_NAME
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
@ -324,11 +323,6 @@ default MAXIMUM_CONSOLE_LOGLEVEL=9
## Select power on after power fail setting
default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
##
## chip name
##
default CONFIG_CHIP_NAME=1
#
# ROMFS
#

4
src/mainboard/msi/ms7135/Config.lb
View File

@ -223,9 +223,7 @@ end
##
## Include the secondary configuration files
##
if CONFIG_CHIP_NAME
config chip.h
end
config chip.h
chip northbridge/amd/amdk8/root_complex # Root complex
device apic_cluster 0 on # APIC cluster

1
src/mainboard/msi/ms7135/Options.lb
View File

@ -77,7 +77,6 @@ uses CONFIG_CONSOLE_SERIAL8250
uses CONFIG_CONSOLE_BTEXT
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK

2
src/mainboard/msi/ms7135/mainboard.c
View File

@ -21,8 +21,6 @@
#include <device/device.h>
#include "chip.h"
#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("MSI MS7135 Mainboard")
};
#endif

4
src/mainboard/msi/ms7260/Config.lb
View File

@ -164,9 +164,7 @@ if USE_DCACHE_RAM
end
end
if CONFIG_CHIP_NAME
config chip.h
end
config chip.h
chip northbridge/amd/amdk8/root_complex # Root complex
device apic_cluster 0 on # APIC cluster

2
src/mainboard/msi/ms7260/Options.lb
View File

@ -74,7 +74,6 @@ uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses CONFIG_USBDEBUG_DIRECT
@ -120,7 +119,6 @@ default CONFIG_LOGICAL_CPUS = 1
default ENABLE_APIC_EXT_ID = 0
default APIC_ID_OFFSET = 0x10
default LIFT_BSP_APIC_ID = 1
default CONFIG_CHIP_NAME = 1
# Move the default coreboot CMOS range off of AMD RTC registers.
default LB_CKS_RANGE_START = 49

2
src/mainboard/msi/ms7260/mainboard.c
View File

@ -21,8 +21,6 @@
#include <device/device.h>
#include "chip.h"
#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("MSI K9N Neo (MS-7260) Mainboard")
};
#endif

4
src/mainboard/msi/ms9185/Config.lb
View File

@ -172,9 +172,7 @@ end
##
## Include the secondary Configuration files
##
if CONFIG_CHIP_NAME
config chip.h
end
config chip.h
# sample config for amd/serengeti_cheetah
chip northbridge/amd/amdk8/root_complex

4
src/mainboard/msi/ms9185/Options.lb
View File

@ -78,7 +78,6 @@ uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
@ -180,9 +179,6 @@ default ENABLE_APIC_EXT_ID=0
default APIC_ID_OFFSET=0x8
default LIFT_BSP_APIC_ID=1
#CHIP_NAME ?
default CONFIG_CHIP_NAME=1
#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
#2G
#default HW_MEM_HOLE_SIZEK=0x200000

2
src/mainboard/msi/ms9185/mainboard.c
View File

@ -26,8 +26,6 @@
#include <device/pci_ops.h>
#include "chip.h"
#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("MSI MS-9185 Mainboard")
};
#endif

4
src/mainboard/msi/ms9282/Config.lb
View File

@ -222,9 +222,7 @@ end
##
## Include the secondary Configuration files
##
if CONFIG_CHIP_NAME
config chip.h
end
config chip.h
# sample config for msi/ms9282

4
src/mainboard/msi/ms9282/Options.lb
View File

@ -74,7 +74,6 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
#bx_b001- uses K8_HW_MEM_HOLE_SIZEK
@ -164,9 +163,6 @@ default CONFIG_MAX_CPUS=4
default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=1
#CHIP_NAME ?
#default CONFIG_CHIP_NAME=1
#1G memory hole
#bx_b001- default K8_HW_MEM_HOLE_SIZEK=0x100000

2
src/mainboard/msi/ms9282/mainboard.c
View File

@ -26,8 +26,6 @@
#include <device/pci_ops.h>
#include "chip.h"
#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("MSI MS-9282 Mainboard")
};
#endif

4
src/mainboard/newisys/khepri/Options.lb
View File

@ -51,7 +51,6 @@ uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
@ -121,9 +120,6 @@ default CONFIG_MAX_CPUS=4
default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=1
#CHIP_NAME ?
default CONFIG_CHIP_NAME=1
#1G memory hole
default HW_MEM_HOLE_SIZEK=0x100000

4
src/mainboard/nvidia/l1_2pvv/Config.lb
View File

@ -252,9 +252,7 @@ end
##
## Include the secondary Configuration files
##
if CONFIG_CHIP_NAME
config chip.h
end
config chip.h
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on

4
src/mainboard/nvidia/l1_2pvv/Options.lb
View File

@ -79,7 +79,6 @@ uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_USBDEBUG_DIRECT
uses CONFIG_PCI_ROM_RUN
@ -193,9 +192,6 @@ default ENABLE_APIC_EXT_ID=0
default APIC_ID_OFFSET=0x10
default LIFT_BSP_APIC_ID=1
#CHIP_NAME ?
default CONFIG_CHIP_NAME=1
#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
#2G
#default HW_MEM_HOLE_SIZEK=0x200000

2
src/mainboard/nvidia/l1_2pvv/mainboard.c
View File

@ -26,8 +26,6 @@
#include <device/pci_ops.h>
#include "chip.h"
#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("NVIDIA l1_2pvv Mainboard")
};
#endif

4
src/mainboard/sunw/ultra40/Config.lb
View File

@ -188,9 +188,7 @@ end
##
## Include the secondary Configuration files
##
if CONFIG_CHIP_NAME
config chip.h
end
config chip.h
# sample config for tyan/s2895
chip northbridge/amd/amdk8/root_complex

4
src/mainboard/sunw/ultra40/Options.lb
View File

@ -52,7 +52,6 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
@ -134,9 +133,6 @@ default CONFIG_MAX_CPUS=4
default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=1
#CHIP_NAME ?
#default CONFIG_CHIP_NAME=1
#1G memory hole
default HW_MEM_HOLE_SIZEK=0x100000

2
src/mainboard/sunw/ultra40/mainboard.c
View File

@ -1,9 +1,7 @@
#include <device/device.h>
#include "chip.h"
#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("Sun Ultra 40 Mainboard")
};
#endif

4
src/mainboard/supermicro/h8dme/Config.lb
View File

@ -218,9 +218,7 @@ end
##
## Include the secondary Configuration files
##
if CONFIG_CHIP_NAME
config chip.h
end
config chip.h
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on

4
src/mainboard/supermicro/h8dme/Options.lb
View File

@ -79,7 +79,6 @@ uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
@ -192,9 +191,6 @@ default ENABLE_APIC_EXT_ID=0
default APIC_ID_OFFSET=0x10
default LIFT_BSP_APIC_ID=1
#CHIP_NAME ?
default CONFIG_CHIP_NAME=1
#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
#2G
#default HW_MEM_HOLE_SIZEK=0x200000

2
src/mainboard/supermicro/h8dme/mainboard.c
View File

@ -23,8 +23,6 @@
#include <device/pci_ops.h>
#include "chip.h"
#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("Supermicro H8DME Mainboard")
};
#endif

4
src/mainboard/supermicro/h8dmr/Config.lb
View File

@ -221,9 +221,7 @@ end
##
## Include the secondary Configuration files
##
if CONFIG_CHIP_NAME
config chip.h
end
config chip.h
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on

4
src/mainboard/supermicro/h8dmr/Options.lb
View File

@ -79,7 +79,6 @@ uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
@ -192,9 +191,6 @@ default ENABLE_APIC_EXT_ID=0
default APIC_ID_OFFSET=0x10
default LIFT_BSP_APIC_ID=1
#CHIP_NAME ?
default CONFIG_CHIP_NAME=1
#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
#2G
#default HW_MEM_HOLE_SIZEK=0x200000

2
src/mainboard/supermicro/h8dmr/mainboard.c
View File

@ -26,8 +26,6 @@
#include <device/pci_ops.h>
#include "chip.h"
#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("Supermicro H8DMR Mainboard")
};
#endif

5
src/mainboard/technologic/ts5300/Options.lb
View File

@ -39,7 +39,6 @@ uses OBJCOPY
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_SERIAL8250
@ -137,10 +136,6 @@ default CONFIG_ROM_PAYLOAD = 1
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
default CONFIG_CHIP_NAME = 1
#
# ROMFS
#

5
src/mainboard/tyan/s2735/Config.lb
View File

@ -175,10 +175,7 @@ end
##
## Include the secondary Configuration files
##
if CONFIG_CHIP_NAME
config chip.h
end
config chip.h
# sample config for tyan/s2735
chip northbridge/intel/e7501

1
src/mainboard/tyan/s2735/Options.lb
View File

@ -56,7 +56,6 @@ uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses CONFIG_CONSOLE_BTEXT
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN

2
src/mainboard/tyan/s2735/mainboard.c
View File

@ -1,9 +1,7 @@
#include <device/device.h>
#include "chip.h"
#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("Tyan S2735 Mainboard")
};
#endif

4
src/mainboard/tyan/s2850/Config.lb
View File

@ -185,9 +185,7 @@ end
##
## Include the secondary Configuration files
##
if CONFIG_CHIP_NAME
config chip.h
end
config chip.h
# sample config for tyan/s2850
chip northbridge/amd/amdk8/root_complex

4
src/mainboard/tyan/s2850/Options.lb
View File

@ -52,7 +52,6 @@ uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
@ -122,9 +121,6 @@ default CONFIG_MAX_CPUS=2
default CONFIG_MAX_PHYSICAL_CPUS=1
default CONFIG_LOGICAL_CPUS=1
#CHIP_NAME ?
default CONFIG_CHIP_NAME=1
#1G memory hole
default HW_MEM_HOLE_SIZEK=0x100000

2
src/mainboard/tyan/s2850/mainboard.c
View File

@ -1,9 +1,7 @@
#include <device/device.h>
#include "chip.h"
#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("Tyan S2850 Mainboard")
};
#endif

4
src/mainboard/tyan/s2875/Config.lb
View File

@ -185,9 +185,7 @@ end
##
## Include the secondary Configuration files
##
if CONFIG_CHIP_NAME
config chip.h
end
config chip.h
# sample config for tyan/s2875
chip northbridge/amd/amdk8/root_complex

4
src/mainboard/tyan/s2875/Options.lb
View File

@ -52,7 +52,6 @@ uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
@ -123,9 +122,6 @@ default CONFIG_MAX_CPUS=4
default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=1
#CHIP_NAME ?
default CONFIG_CHIP_NAME=1
#1G memory hole
default HW_MEM_HOLE_SIZEK=0x100000

2
src/mainboard/tyan/s2875/mainboard.c
View File

@ -1,9 +1,7 @@
#include <device/device.h>
#include "chip.h"
#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("Tyan S2875 Mainboard")
};
#endif

4
src/mainboard/tyan/s2880/Config.lb
View File

@ -185,9 +185,7 @@ end
##
## Include the secondary Configuration files
##
if CONFIG_CHIP_NAME
config chip.h
end
config chip.h
# sample config for tyan/s2880
chip northbridge/amd/amdk8/root_complex

4
src/mainboard/tyan/s2880/Options.lb
View File

@ -52,7 +52,6 @@ uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
@ -122,9 +121,6 @@ default CONFIG_MAX_CPUS=2
default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=0
#CHIP_NAME ?
default CONFIG_CHIP_NAME=1
#1G memory hole
default HW_MEM_HOLE_SIZEK=0x100000

2
src/mainboard/tyan/s2880/mainboard.c
View File

@ -1,9 +1,7 @@
#include <device/device.h>
#include "chip.h"
#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("Tyan S2880 Mainboard")
};
#endif

4
src/mainboard/tyan/s2881/Config.lb
View File

@ -185,9 +185,7 @@ end
##
## Include the secondary Configuration files
##
if CONFIG_CHIP_NAME
config chip.h
end
config chip.h
# sample config for tyan/s2881
chip northbridge/amd/amdk8/root_complex

4
src/mainboard/tyan/s2881/Options.lb
View File

@ -52,7 +52,6 @@ uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
@ -127,9 +126,6 @@ default CONFIG_MAX_CPUS=4
default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=1
#CHIP_NAME ?
default CONFIG_CHIP_NAME=1
##HT Unit ID offset, default is 1, the typical one
default HT_CHAIN_UNITID_BASE=0x0a

2
src/mainboard/tyan/s2881/mainboard.c
View File

@ -158,9 +158,7 @@ static void enable_dev(struct device *dev)
dev->ops = &mainboard_operations;
}
#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("Tyan S2881 Mainboard")
.enable_dev = enable_dev,
};
#endif

4
src/mainboard/tyan/s2882/Config.lb
View File

@ -185,9 +185,7 @@ end
##
## Include the secondary Configuration files
##
if CONFIG_CHIP_NAME
config chip.h
end
config chip.h
# sample config for tyan/s2882
chip northbridge/amd/amdk8/root_complex

4
src/mainboard/tyan/s2882/Options.lb
View File

@ -52,7 +52,6 @@ uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
@ -122,9 +121,6 @@ default CONFIG_MAX_CPUS=4
default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=1
#CHIP_NAME ?
default CONFIG_CHIP_NAME=1
#1G memory hole
default HW_MEM_HOLE_SIZEK=0x100000

2
src/mainboard/tyan/s2882/mainboard.c
View File

@ -1,9 +1,7 @@
#include <device/device.h>
#include "chip.h"
#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("Tyan S2882 Mainboard")
};
#endif

4
src/mainboard/tyan/s2885/Config.lb
View File

@ -185,9 +185,7 @@ end
##
## Include the secondary Configuration files
##
if CONFIG_CHIP_NAME
config chip.h
end
config chip.h
# sample config for tyan/s2885
chip northbridge/amd/amdk8/root_complex

4
src/mainboard/tyan/s2885/Options.lb
View File

@ -52,7 +52,6 @@ uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
@ -133,9 +132,6 @@ default CONFIG_MAX_CPUS=4
default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=1
#CHIP_NAME ?
default CONFIG_CHIP_NAME=1
##HT Unit ID offset, default is 1, the typical one
default HT_CHAIN_UNITID_BASE=0x0a

2
src/mainboard/tyan/s2885/mainboard.c
View File

@ -1,9 +1,7 @@
#include <device/device.h>
#include "chip.h"
#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("Tyan S2885 Mainboard")
};
#endif

4
src/mainboard/tyan/s2891/Config.lb
View File

@ -205,9 +205,7 @@ end
##
## Include the secondary Configuration files
##
if CONFIG_CHIP_NAME
config chip.h
end
config chip.h
# sample config for tyan/s2891
chip northbridge/amd/amdk8/root_complex

1
src/mainboard/tyan/s2891/Options.lb
View File

@ -59,7 +59,6 @@ uses CONFIG_CONSOLE_SERIAL8250
uses CONFIG_CONSOLE_BTEXT
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_VGA_ROM_RUN
uses CONFIG_PCI_ROM_RUN

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