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sb/intel/lynxpoint: Move S3 check out of `early_pch_init` 

Done for consistency with other platforms. This also drops redundant S3
resume logging, as `southbridge_detect_s3_resume` already prints it.

Tested on Asrock B85M Pro4, still boots and still resumes from S3.

Change-Id: Id96c5aedad80702ebf343dd0a351fbd4e7b1c6c1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Angel Pons 2021-03-12 13:06:45 +01:00 committed by Patrick Georgi
parent 0b39379c9c
commit 30931f5a4d
3 changed files with 9 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
src/northbridge/intel/haswell/romstage.c
View File

@ -5,6 +5,7 @@
#include <cf9_reset.h>
#include <device/device.h>
#include <device/mmio.h>
#include <elog.h>
#include <timestamp.h>
#include <cpu/x86/lapic.h>
#include <cbmem.h>
@ -16,6 +17,7 @@
#include <northbridge/intel/haswell/chip.h>
#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/raminit.h>
#include <southbridge/intel/common/pmclib.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <southbridge/intel/lynxpoint/me.h>
#include <string.h>
@ -47,8 +49,6 @@ void mainboard_romstage_entry(void)
const struct northbridge_intel_haswell_config *cfg = config_of_soc();
int s3resume;
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
@ -76,7 +76,11 @@ void mainboard_romstage_entry(void)
enable_lapic();
s3resume = early_pch_init();
early_pch_init();
const int s3resume = southbridge_detect_s3_resume();
elog_boot_notify(s3resume);
/* Perform some early chipset initialization required
* before RAM initialization can work
@ -84,15 +88,6 @@ void mainboard_romstage_entry(void)
haswell_early_initialization();
printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n");
if (s3resume) {
#if CONFIG(HAVE_ACPI_RESUME)
printk(BIOS_DEBUG, "Resume from S3 detected.\n");
#else
printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
s3resume = 0;
#endif
}
/* Prepare USB controller early in S3 resume */
if (s3resume)
enable_usb_bar();

12
src/southbridge/intel/lynxpoint/early_pch.c
View File

@ -6,7 +6,6 @@
#include <device/pci_def.h>
#include <device/smbus_host.h>
#include <southbridge/intel/common/pmbase.h>
#include <southbridge/intel/common/pmclib.h>
#include <elog.h>
#include "pch.h"
#include "chip.h"
@ -86,10 +85,8 @@ void __weak mainboard_config_superio(void)
{
}
int early_pch_init(void)
void early_pch_init(void)
{
int wake_from_s3;
pch_enable_bars();
#if CONFIG(INTEL_LYNXPOINT_LP)
@ -123,11 +120,4 @@ int early_pch_init(void)
RCBA32(0x2324) = 0x00854c74;
}
wake_from_s3 = southbridge_detect_s3_resume();
elog_boot_notify(wake_from_s3);
/* Report if we are waking from s3. */
return wake_from_s3;
}

2
src/southbridge/intel/lynxpoint/pch.h
View File

@ -121,7 +121,7 @@ void pch_log_state(void);
void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
void enable_usb_bar(void);
int early_pch_init(void);
void early_pch_init(void);
void pch_enable_lpc(void);
void mainboard_config_superio(void);
void mainboard_config_rcba(void);