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sandybridge: Add native sandybridge 

Change-Id: I1b51310b4387e588c4828563620b0e2770598503
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6753
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Vladimir Serbinenko 2014-08-24 22:35:29 +02:00
parent 3a2310e05c
commit 309fc4ce8b
8 changed files with 24 additions and 8 deletions
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1
src/cpu/intel/Makefile.inc
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@ -18,6 +18,7 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_RPGA988B) += socket_rPGA988B
subdirs-$(CONFIG_CPU_INTEL_SOCKET_RPGA989) += socket_rPGA989 subdirs-$(CONFIG_CPU_INTEL_SOCKET_RPGA989) += socket_rPGA989
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += model_2065x subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += model_2065x
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += model_206ax
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += model_206ax subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += model_206ax
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += model_206ax subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += model_206ax
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell

2
src/cpu/x86/smm/smmhandler_tseg.S
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@ -57,7 +57,7 @@
#define SMI_UNLOCKED 1 #define SMI_UNLOCKED 1
#define __PRE_RAM__ #define __PRE_RAM__
#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE #if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE || CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) #define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
#elif CONFIG_NORTHBRIDGE_INTEL_NEHALEM #elif CONFIG_NORTHBRIDGE_INTEL_NEHALEM

4
src/cpu/x86/smm/smmrelocate.S
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@ -48,7 +48,7 @@
#if CONFIG_SMM_TSEG #if CONFIG_SMM_TSEG
#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE #if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE || CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) #define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
#elif CONFIG_NORTHBRIDGE_INTEL_NEHALEM #elif CONFIG_NORTHBRIDGE_INTEL_NEHALEM
@ -195,7 +195,7 @@ smm_relocate:
xorl %edx, %edx xorl %edx, %edx
wrmsr wrmsr
#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE #if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE || CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE
/* /*
* IED base is top 4M of TSEG * IED base is top 4M of TSEG
*/ */

1
src/northbridge/intel/Makefile.inc
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@ -14,6 +14,7 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SCH) += sch
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I5000) += i5000 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I5000) += i5000
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += nehalem subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += nehalem
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += sandybridge subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += sandybridge
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += sandybridge
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += sandybridge subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += sandybridge
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += sandybridge subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += sandybridge
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell

16
src/northbridge/intel/sandybridge/Kconfig
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@ -25,6 +25,14 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE
select DYNAMIC_CBMEM select DYNAMIC_CBMEM
select CPU_INTEL_MODEL_206AX select CPU_INTEL_MODEL_206AX
config NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE
bool
select CACHE_MRC_BIN
select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT
select CPU_INTEL_MODEL_206AX
select HAVE_DEBUG_RAM_SETUP
config NORTHBRIDGE_INTEL_IVYBRIDGE config NORTHBRIDGE_INTEL_IVYBRIDGE
bool bool
select CACHE_MRC_BIN select CACHE_MRC_BIN
@ -41,7 +49,7 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE
select CPU_INTEL_MODEL_306AX select CPU_INTEL_MODEL_306AX
select HAVE_DEBUG_RAM_SETUP select HAVE_DEBUG_RAM_SETUP
if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE || NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE
config VGA_BIOS_ID config VGA_BIOS_ID
string string
@ -66,8 +74,10 @@ config MRC_CACHE_SIZE
config DCACHE_RAM_BASE config DCACHE_RAM_BASE
hex hex
default 0xff7e0000 if !NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE default 0xff7e0000 if NORTHBRIDGE_INTEL_IVYBRIDGE
default 0xff7e0000 if NORTHBRIDGE_INTEL_SANDYBRIDGE
default 0xfefe0000 if NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE default 0xfefe0000 if NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE
default 0xfefe0000 if NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE
config DCACHE_RAM_SIZE config DCACHE_RAM_SIZE
hex hex
@ -83,7 +93,7 @@ config DCACHE_RAM_MRC_VAR_SIZE
config HAVE_MRC config HAVE_MRC
bool "Add a System Agent binary" bool "Add a System Agent binary"
depends on !NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE depends on !NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE && !NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE
help help
Select this option to add a System Agent binary to Select this option to add a System Agent binary to
the resulting coreboot image. the resulting coreboot image.

3
src/northbridge/intel/sandybridge/Makefile.inc
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@ -31,6 +31,8 @@ romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += raminit.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += raminit.c romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += raminit.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += raminit_native.c romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += raminit_native.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += ../../../device/dram/ddr3.c romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += ../../../device/dram/ddr3.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += raminit_native.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += ../../../device/dram/ddr3.c
romstage-y += mrccache.c romstage-y += mrccache.c
romstage-y += early_init.c romstage-y += early_init.c
romstage-y += report_platform.c romstage-y += report_platform.c
@ -56,6 +58,7 @@ mrc.cache-file := $(obj)/mrc.cache
mrc-cache-position-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) := 0xfffd0000 mrc-cache-position-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) := 0xfffd0000
mrc-cache-position-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) := 0xfffd0000 mrc-cache-position-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) := 0xfffd0000
mrc-cache-position-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) := 0xfffe0000 mrc-cache-position-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) := 0xfffe0000
mrc-cache-position-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) := 0xfffe0000
mrc.cache-position := $(mrc-cache-position-y) mrc.cache-position := $(mrc-cache-position-y)
mrc.cache-type := 0xac mrc.cache-type := 0xac
endif endif

1
src/southbridge/intel/bd82x6x/Makefile.inc
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@ -52,6 +52,7 @@ romstage-y += early_spi.c early_pch.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += early_me.c romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += early_me.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += early_me.c romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += early_me.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += early_thermal.c early_pch_native.c early_me_native.c romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += early_thermal.c early_pch_native.c early_me_native.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += early_thermal.c early_pch_native.c early_me_native.c
ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
IFD_BIN_PATH := $(objgenerated)/ifdfake.bin IFD_BIN_PATH := $(objgenerated)/ifdfake.bin

4
src/southbridge/intel/bd82x6x/usb_ehci.c
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@ -39,7 +39,7 @@ static void usb_ehci_init(struct device *dev)
printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
/* For others, done in MRC. */ /* For others, done in MRC. */
#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) #if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) || IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE)
pci_write_config32(dev, 0x84, 0x930c8811); pci_write_config32(dev, 0x84, 0x930c8811);
pci_write_config32(dev, 0x88, 0x24000d30); pci_write_config32(dev, 0x88, 0x24000d30);
pci_write_config32(dev, 0xf4, 0x80408588); pci_write_config32(dev, 0xf4, 0x80408588);
@ -54,7 +54,7 @@ static void usb_ehci_init(struct device *dev)
pci_write_config32(dev, PCI_COMMAND, reg32); pci_write_config32(dev, PCI_COMMAND, reg32);
/* For others, done in MRC. */ /* For others, done in MRC. */
#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) #if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) || IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE)
struct resource *res; struct resource *res;
u8 access_cntl; u8 access_cntl;