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mb/google/dedede: Override GPIO PM configuration 

If Cr50 is running old firmware version and hence does not ensure long
interrupt pulses, override the GPIO PM configuration.

BUG=None
TEST=Build and boot waddledee to OS. Ensure that any chip override
happens before FSP silicon parameter initialization. Ensure that the
suspend/resume sequence works fine. Ensure that the reboot sequence
works fine for 50 iterations.

Change-Id: I455c51d4a63b1b5edadbf00c786ce61b0ba1ff00
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Karthikeyan Ramasubramanian 2020-09-29 22:06:26 -06:00 committed by Karthik Ramasubramanian
parent 9765394663
commit 30b854dccd
3 changed files with 25 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/google/dedede/Kconfig
View File

@ -1,6 +1,7 @@
config BOARD_GOOGLE_BASEBOARD_DEDEDE
def_bool n
select BOARD_ROMSIZE_KB_16384 if !BOARD_ROMSIZE_KB_32768
select CR50_USE_LONG_INTERRUPT_PULSES
select DPTF_USE_EISA_HID
select DRIVERS_I2C_GENERIC
select DRIVERS_I2C_HID

24
src/mainboard/google/dedede/mainboard.c
View File

@ -4,9 +4,31 @@
#include <bootstate.h>
#include <baseboard/variants.h>
#include <device/device.h>
#include <drivers/spi/tpm/tpm.h>
#include <ec/ec.h>
#include <security/tpm/tss.h>
#include <soc/soc_chip.h>
#include <vendorcode/google/chromeos/chromeos.h>
static void mainboard_update_soc_chip_config(void)
{
struct soc_intel_jasperlake_config *cfg = config_of_soc();
int ret;
ret = tlcl_lib_init();
if (ret != VB2_SUCCESS) {
printk(BIOS_ERR, "tlcl_lib_init() failed: 0x%x\n", ret);
return;
}
if (!cr50_is_long_interrupt_pulse_enabled()) {
/* Disable GPIO PM to allow for shorter IRQ pulses */
printk(BIOS_INFO, "Override GPIO PM\n");
cfg->gpio_override_pm = 1;
memset(cfg->gpio_pm, 0, sizeof(cfg->gpio_pm));
}
}
__weak void variant_isst_override(void)
{
/*
@ -31,6 +53,8 @@ static void mainboard_init(void *chip_info)
gpio_configure_pads_with_override(base_pads, base_num,
override_pads, override_num);
mainboard_update_soc_chip_config();
}
static void mainboard_dev_init(struct device *dev)

8
src/mainboard/google/dedede/variants/baseboard/devicetree.cb
View File

@ -129,14 +129,6 @@ chip soc/intel/jasperlake
# Select eDP for port A
register "DdiPortAConfig" = "1"
# Disable PM to allow for shorter irq pulses
register "gpio_override_pm" = "1"
register "gpio_pm[0]" = "0"
register "gpio_pm[1]" = "0"
register "gpio_pm[2]" = "0"
register "gpio_pm[3]" = "0"
register "gpio_pm[4]" = "0"
# Enable HPD for DDI ports B/C
register "DdiPortBHpd" = "1"
register "DdiPortCHpd" = "1"