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haswell: notes and updates. 

Add a FIXME about checking a MCHBAR register that isn't setup yet.
Also, remove revision updating because I can't find anything in the
docs that suggest this is required for haswell.

Change-Id: Ia8a6e08f82e18789e31c6c2ec2c1d63740c18dc4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2631
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Aaron Durbin 2012-11-29 17:21:51 -06:00 committed by Ronald G. Minnich
parent 8256a9b715
commit 30c3900451
2 changed files with 4 additions and 15 deletions
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4
src/mainboard/intel/graysreef/romstage.c
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@ -193,6 +193,10 @@ void main(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
/*
* FIXME: MCHBAR isn't setup yet. It's setup in
* haswell_early_initialization().
*/
if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, "soft reset detected\n");
boot_mode = 1;

15
src/northbridge/intel/haswell/early_init.c
View File

@ -139,21 +139,6 @@ static void haswell_setup_graphics(void)
void haswell_early_initialization(int chipset_type)
{
u32 capid0_a;
u8 reg8;
/* Device ID Override Enable should be done very early */
capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4);
if (capid0_a & (1 << 10)) {
reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf3);
reg8 &= ~7; /* Clear 2:0 */
if (chipset_type == HASWELL_MOBILE)
reg8 |= 1; /* Set bit 0 */
pci_write_config8(PCI_DEV(0, 0, 0), 0xf3, reg8);
}
/* Setup all BARs required for early PCIe and raminit */
haswell_setup_bars();