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soc/intel/skylake: acpi: drop HWP's dependency on EIST 

Enhanced Intel SpeedStep Technology (EIST) and Intel Speed Shift
Technology (ISST) - also know as HWP - are two independent mechanisms
for controlling voltage and frequency based on performance hints.

When HWP is enabled, it overrides the software-based EIST. It does not
depend on EIST, though, but can be enabled on its own.

Break up that currently existing dependency in ACPI generation code.

It was tested that HWP can be enabled and gets used by the Linux pstate
cpufreq driver. With HWP disabled, the frequency does not decrease, even
not in powersave mode. After enabling HWP the frequency changed in
relation to the current workload. (Test device: Acer ES1-572)

Change-Id: I93d888ddce7b54e91b54e5b4fdd4d9cf16630eda
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44137
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michael Niewöhner 2020-08-03 15:01:18 +02:00
parent fa0080d187
commit 30c5d21891
1 changed files with 5 additions and 3 deletions
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8
src/soc/intel/skylake/acpi.c
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@ -379,7 +379,7 @@ void generate_cpu_entries(const struct device *device)
printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n",
numcpus, cores_per_package);
if (config->eist_enable && config->speed_shift_enable) {
if (config->speed_shift_enable) {
struct cppc_config cppc_config;
cpu_init_cppc_config(&cppc_config, 2 /* version 2 */);
acpigen_write_CPPC_package(&cppc_config);
@ -403,9 +403,11 @@ void generate_cpu_entries(const struct device *device)
/* Generate P-state tables */
generate_p_state_entries(core_id,
cores_per_package);
if (config->speed_shift_enable)
acpigen_write_CPPC_method();
}
if (config->speed_shift_enable)
acpigen_write_CPPC_method();
acpigen_pop_len();
}
}