- Add back in the hard reset code from the freebios1 tree.
This allows generic code to reset the box. - Update the hypertransport code to automatically calculate link widths and freequencies, and to call hard_reset if neecessary for the changes to go into effect. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1094 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Eric Biederman
parent
9bdb460a97
commit
30e143a5f0
4
NEWS
4
NEWS
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@ -1,3 +1,7 @@
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- 1.1.2
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Add back in the hard_reset method from freebios1 this allows generic
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code to reset the box. The hypertransport setup code now uses it to
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reset the box when the hypertransport link speeds need to change.
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- 1.1.1
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Updates to the new configuration system so it works more reliably
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Removed a bunch of unused configuration variables
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@ -40,9 +40,7 @@ it with the version available from LANL.
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#if 0
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#include <part/mainboard.h>
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#endif
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#if 0
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#include <part/hard_reset.h>
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#endif
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#include <smp/atomic.h>
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#include <boot/elf.h>
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@ -160,12 +158,10 @@ void hardwaremain(int boot_complete)
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post_code(0x40);
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#if 0
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/* If we have already booted attempt a hard reboot */
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if (boot_complete) {
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hard_reset();
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}
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#endif
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init_timer(); /* needs to be moved into static configuration */
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CONFIGURE(CONF_PASS_PRE_PCI);
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@ -17,6 +17,7 @@
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <part/fallback_boot.h>
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/** Given a device and register, read the size of the BAR for that register.
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* @param dev Pointer to the device structure
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@ -459,6 +460,157 @@ static struct device *pci_scan_get_dev(struct device **list, unsigned int devfn)
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return dev;
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}
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void assign_id_set_links(device_t dev, uint8_t *pos,
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uint8_t *previous_pos, unsigned previous_unitid,
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unsigned last_unitid, int *reset_needed,
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struct device *bus, unsigned *next_unitid)
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{
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static const uint8_t link_width_to_pow2[]= { 3, 4, 0, 5, 1, 2, 0, 0 };
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static const uint8_t pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 };
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uint16_t flags;
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struct device last, prev_bus, previous;
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unsigned count;
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uint8_t present_width_cap;
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uint16_t present_freq_cap;
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uint8_t upstream_width_cap;
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uint16_t upstream_freq_cap;
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uint8_t ln_upstream_width_in, ln_present_width_in;
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uint8_t ln_upstream_width_out, ln_present_width_out;
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uint16_t mask;
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uint8_t freq;
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uint8_t old_freq;
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uint8_t upstream_width, present_width;
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uint8_t old_width;
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flags = pci_read_config16(dev, (*pos) + PCI_CAP_FLAGS);
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printk_debug("flags: 0x%04x\n", (unsigned)flags);
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if ((flags >> 13) != 0)
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return; /* Entry is a Host */
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/* Entry is a Slave secondary */
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flags &= ~0x1f; /* mask out base unit ID */
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flags |= *next_unitid & 0x1f; /* assign ID */
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count = (flags >> 5) & 0x1f; /* get unit count */
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printk_debug("unitid: 0x%02x, count: 0x%02x\n",
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*next_unitid, count);
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pci_write_config16(dev, (*pos) + PCI_CAP_FLAGS, flags);
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*next_unitid += count;
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if (previous_unitid == 0) { /* the link is back to the host */
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prev_bus.secondary = 0;
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/* calculate the previous pos for the host */
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*previous_pos = 0x80;
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previous.bus = &prev_bus;
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previous.devfn = 0x18 << 3;
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#warning "FIXME we should not hard code this!"
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} else {
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previous.bus = bus;
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previous.devfn = previous_unitid << 3;
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}
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last.bus = bus;
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last.devfn = last_unitid << 3;
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/* Set link width and frequency */
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present_freq_cap = pci_read_config16(&last,
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(*pos) + PCI_HT_CAP_SLAVE_FREQ_CAP0);
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present_width_cap = pci_read_config8(&last,
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(*pos) + PCI_HT_CAP_SLAVE_WIDTH0);
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if(previous_unitid == 0) { /* the link is back to the host */
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upstream_freq_cap = pci_read_config16(&previous,
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(*previous_pos) + PCI_HT_CAP_HOST_FREQ_CAP);
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upstream_width_cap = pci_read_config8(&previous,
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(*previous_pos) + PCI_HT_CAP_HOST_WIDTH);
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}
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else { /* The link is back up the chain */
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upstream_freq_cap = pci_read_config16(&previous,
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(*previous_pos) + PCI_HT_CAP_SLAVE_FREQ_CAP1);
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upstream_width_cap = pci_read_config8(&previous,
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(*previous_pos) + PCI_HT_CAP_SLAVE_WIDTH1);
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}
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/* Calculate the highest possible frequency */
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/* Errata for 8131 - freq 5 has hardware problems don't support it */
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freq = log2(present_freq_cap & upstream_freq_cap & 0x1f);
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/* Calculate the highest width */
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ln_upstream_width_in = link_width_to_pow2[upstream_width_cap & 7];
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ln_present_width_out = link_width_to_pow2[(present_width_cap >> 4) & 7];
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if (ln_upstream_width_in > ln_present_width_out) {
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ln_upstream_width_in = ln_present_width_out;
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}
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upstream_width = pow2_to_link_width[ln_upstream_width_in];
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present_width = pow2_to_link_width[ln_upstream_width_in] << 4;
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ln_upstream_width_out = link_width_to_pow2[(upstream_width_cap >> 4) & 7];
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ln_present_width_in = link_width_to_pow2[present_width_cap & 7];
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if (ln_upstream_width_out > ln_present_width_in) {
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ln_upstream_width_out = ln_present_width_in;
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}
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upstream_width |= pow2_to_link_width[ln_upstream_width_out] << 4;
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present_width |= pow2_to_link_width[ln_upstream_width_out];
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/* set the present device */
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old_freq = pci_read_config8(&last, (*pos) + PCI_HT_CAP_SLAVE_FREQ0);
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if(old_freq != freq) {
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pci_write_config8(&last,
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(*pos) + PCI_HT_CAP_SLAVE_FREQ0, freq);
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*reset_needed = 1;
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printk_debug("HyperT FreqP old %x new %x\n",old_freq,freq);
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}
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old_width = pci_read_config8(&last,
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(*pos) + PCI_HT_CAP_SLAVE_WIDTH0 + 1);
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if(present_width != old_width) {
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pci_write_config8(&last,
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(*pos) + PCI_HT_CAP_SLAVE_WIDTH0 + 1, present_width);
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*reset_needed = 1;
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printk_debug("HyperT widthP old %x new %x\n",
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old_width, present_width);
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}
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/* set the upstream device */
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if(previous_unitid == 0) { /* the link is back to the host */
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old_freq = pci_read_config8(&previous,
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(*previous_pos) + PCI_HT_CAP_HOST_FREQ);
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old_freq &= 0x0f;
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if(freq != old_freq) {
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pci_write_config8(&previous,
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(*previous_pos) + PCI_HT_CAP_HOST_FREQ, freq);
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*reset_needed = 1;
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printk_debug("HyperT freqUH old %x new %x\n",
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old_freq, freq);
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}
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old_width = pci_read_config8(&previous,
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(*previous_pos) + PCI_HT_CAP_HOST_WIDTH + 1);
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if(upstream_width != old_width) {
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pci_write_config8(&previous,
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(*previous_pos) + PCI_HT_CAP_HOST_WIDTH + 1,
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upstream_width);
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*reset_needed = 1;
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printk_debug("HyperT widthUH old %x new %x\n",
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old_width, upstream_width);
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}
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}
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else { /* The link is back up the chain */
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old_freq = pci_read_config8(&previous,
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(*previous_pos) + PCI_HT_CAP_SLAVE_FREQ1);
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old_freq &= 0x0f;
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if(freq != old_freq) {
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pci_write_config8(&previous,
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(*previous_pos) + PCI_HT_CAP_SLAVE_FREQ1,
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freq);
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*reset_needed = 1;
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printk_debug("HyperT freqUL old %x new %x\n",
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old_freq, freq);
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}
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old_width = pci_read_config8(&previous,
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(*previous_pos) + PCI_HT_CAP_SLAVE_WIDTH1 + 1);
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if(upstream_width != old_width) {
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pci_write_config8(&previous,
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(*previous_pos) + PCI_HT_CAP_SLAVE_WIDTH1,
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upstream_width);
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*reset_needed = 1;
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printk_debug("HyperT widthUL old %x new %x\n",
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old_width, upstream_width);
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}
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}
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*previous_pos = *pos;
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*pos=0;
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}
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#define HYPERTRANSPORT_SUPPORT 1
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/** Scan the pci bus devices and bridges.
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@ -474,7 +626,8 @@ unsigned int pci_scan_bus(struct device *bus, unsigned int max)
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struct device *child;
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#if HYPERTRANSPORT_SUPPORT
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unsigned next_unitid, last_unitid, previous_unitid;
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int reset_needed;
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int reset_needed = 0;
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uint8_t previous_pos;
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#endif
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printk_debug("PCI: pci_scan_bus for bus %d\n", bus->secondary);
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@ -518,12 +671,15 @@ unsigned int pci_scan_bus(struct device *bus, unsigned int max)
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printk_debug("Capability: 0x%02x @ 0x%02x\n", cap, pos);
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if (cap == PCI_CAP_ID_HT) {
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uint16_t flags;
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flags = pci_read_config16(&dummy, pos + PCI_CAP_FLAGS);
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printk_debug("flags: 0x%04x\n", (unsigned)flags);
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flags = pci_read_config16(&dummy,
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pos + PCI_CAP_FLAGS);
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printk_debug("flags: 0x%04x\n",
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(unsigned)flags);
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if ((flags >> 13) == 0) {
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/* Clear the unitid */
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flags &= ~0x1f;
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pci_write_config16(&dummy, pos + PCI_CAP_FLAGS, flags);
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pci_write_config16(&dummy,
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pos + PCI_CAP_FLAGS, flags);
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break;
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}
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}
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@ -533,10 +689,11 @@ unsigned int pci_scan_bus(struct device *bus, unsigned int max)
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/* If present assign unitid to a hypertransport chain */
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last_unitid = 0;
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next_unitid = 1;
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previous_pos = 0;
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do {
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struct device dummy;
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uint32_t id;
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uint8_t hdr_type, pos, previous_pos;
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uint8_t hdr_type, pos;
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previous_unitid = last_unitid;
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last_unitid = next_unitid;
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@ -566,107 +723,24 @@ unsigned int pci_scan_bus(struct device *bus, unsigned int max)
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cap = pci_read_config8(&dummy, pos + PCI_CAP_LIST_ID);
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printk_debug("Capability: 0x%02x @ 0x%02x\n", cap, pos);
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if (cap == PCI_CAP_ID_HT) {
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uint16_t flags;
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uint16_t links;
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flags = pci_read_config16(&dummy, pos + PCI_CAP_FLAGS);
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printk_debug("flags: 0x%04x\n", (unsigned)flags);
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if ((flags >> 13) == 0) { /* Entry is a Slave secondary */
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struct device last, previous;
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unsigned count;
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unsigned width;
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flags &= ~0x1f; /* mask out base unit ID */
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flags |= next_unitid & 0x1f; /* assign ID */
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count = (flags >> 5) & 0x1f; /* get unit count */
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printk_debug("unitid: 0x%02x, count: 0x%02x\n",
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next_unitid, count);
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pci_write_config16(&dummy, pos + PCI_CAP_FLAGS, flags);
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next_unitid += count;
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if (previous_unitid == 0) { /* the link is back to the host */
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/* calculate the previous pos for the host */
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previous_pos = 0x80;
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previous.bus = 0;
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previous.devfn = 0x18 << 3;
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#warning "FIXME we should not hard code this!"
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} else {
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previous.bus = bus;
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previous.devfn = previous_unitid << 3;
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assign_id_set_links(&dummy,&pos,&previous_pos,
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previous_unitid, last_unitid,
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&reset_needed, bus,
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&next_unitid);
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}
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last.bus = bus;
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last.devfn = last_unitid << 3;
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/* Set link width and frequency */
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flags = pci_read_config16(&last, pos + PCI_HT_CAP_SLAVE_FREQ_CAP0);
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cap = pci_read_config8(&last, pos + PCI_HT_CAP_SLAVE_WIDTH0);
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if(previous_unitid == 0) { /* the link is back to the host */
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links = pci_read_config16(&previous,
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previous_pos + PCI_HT_CAP_HOST_FREQ_CAP);
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width = pci_read_config8(&previous,
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previous_pos + PCI_HT_CAP_HOST_WIDTH);
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if(pos)
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pos = pci_read_config8(&dummy,
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pos + PCI_CAP_LIST_NEXT);
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}
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else { /* The link is back up the chain */
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links = pci_read_config16(&previous,
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previous_pos + PCI_HT_CAP_SLAVE_FREQ_CAP1);
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width = pci_read_config8(&previous,
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previous_pos + PCI_HT_CAP_SLAVE_WIDTH1);
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}
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/* Calculate the highest possible frequency */
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links &= flags;
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for(flags = 0x40, count = 6; count; count--, flags >>= 1) {
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if(flags & links) break;
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}
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/* Calculate the highest width */
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width &= cap;
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/* set the present device */
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if(count != pci_read_config8(&last, pos + PCI_HT_CAP_HOST_FREQ)) {
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pci_write_config8(&last, pos + PCI_HT_CAP_HOST_FREQ, count);
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reset_needed = 1;
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}
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if(width != pci_read_config8(&last, pos + PCI_HT_CAP_SLAVE_WIDTH0 + 1)) {
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pci_write_config8(&last,
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pos + PCI_HT_CAP_SLAVE_WIDTH0 + 1, width);
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reset_needed = 1;
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}
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/* set the upstream device */
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if(previous_unitid == 0) { /* the link is back to the host */
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cap = pci_read_config8(&previous, previous_pos + PCI_HT_CAP_HOST_FREQ);
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cap &= 0x0f;
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if(count != cap) {
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pci_write_config8(&previous,
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previous_pos + PCI_HT_CAP_HOST_FREQ, count);
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reset_needed = 1;
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}
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cap = pci_read_config8(&previous, previous_pos + PCI_HT_CAP_HOST_WIDTH + 1);
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if(width != cap) {
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pci_write_config8(&previous,
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previous_pos + PCI_HT_CAP_HOST_WIDTH + 1, width);
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reset_needed = 1;
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}
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}
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else { /* The link is back up the chain */
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cap = pci_read_config8(&previous,
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previous_pos + PCI_HT_CAP_SLAVE_FREQ1);
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cap &= 0x0f;
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if(count != cap) {
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pci_write_config8(&previous,
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previous_pos + PCI_HT_CAP_SLAVE_FREQ1, count);
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reset_needed = 1;
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}
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cap = pci_read_config8(&previous,
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previous_pos + PCI_HT_CAP_SLAVE_WIDTH1 + 1);
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if(width != cap) {
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pci_write_config8(&previous,
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previous_pos + PCI_HT_CAP_SLAVE_WIDTH1, width);
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reset_needed = 1;
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}
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}
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break;
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}
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}
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pos = pci_read_config8(&dummy, pos + PCI_CAP_LIST_NEXT);
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}
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previous_pos = pos;
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} while((last_unitid != next_unitid) && (next_unitid <= 0x1f));
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#if HAVE_HARD_RESET == 1
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if(reset_needed) {
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printk_debug("HyperT reset needed\n");
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boot_successful();
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hard_reset();
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}
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printk_debug("HyperT reset not needed\n");
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#endif /* HAVE_HARD_RESET */
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#endif /* HYPERTRANSPORT_SUPPORT */
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/* probe all devices on this bus with some optimization for non-existance and
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@ -674,7 +748,7 @@ unsigned int pci_scan_bus(struct device *bus, unsigned int max)
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for (devfn = 0; devfn <= 0xff; devfn++) {
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struct device dummy;
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uint32_t id, class;
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uint8_t cmd, tmp, hdr_type;
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uint8_t hdr_type;
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/* First thing setup the device structure */
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dev = pci_scan_get_dev(&old_devices, devfn);
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@ -0,0 +1,11 @@
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#ifndef PART_HARD_RESET_H
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#define PART_HARD_RESET_H
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#if HAVE_HARD_RESET == 1
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void hard_reset(void);
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#else
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#define hard_reset() do {} while(0)
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#endif
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#endif
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