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mb/google/zork: Set vw_irq_polarity from low to high 

The EC used on zork uses a level high interrupt. This change configures
the polarity correctly.

The eSPI config is baked into RO verstage. The zork ToT build doesn't
use signed verstage since it's incompatible with the ToT version of
vboot. This means we can safely switch the keyboard IRQ polarity.

NOTE: Do not cherry pick this into the Zork firmware branch!

BUG=b:160595155
TEST=On morphius verify keyboard works as correctly and no spurious
interrupts are thrown on S0i3 resume. Also verified keyboard and mouse
work correctly in windows.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8d3195522f3bd5e477635494c7156683aae0ff0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
Raul E Rangel 2022-07-29 21:07:36 -06:00 committed by Raul Rangel
parent 74bce48f1d
commit 30edb46e8c
4 changed files with 4 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
View File

@ -227,13 +227,7 @@ chip soc/amd/picasso
.oob_ch_en = 0, .oob_ch_en = 0,
.flash_ch_en = 0, .flash_ch_en = 0,
/* .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1) | ESPI_VW_IRQ_LEVEL_HIGH(12),
* b/160595155 - These should really be ESPI_VW_IRQ_LEVEL_HIGH,
* but eSPI gets configured in verstage which is in RO.
* We have already locked RO for zork devices so we need
* make it so x86 coreboot re-initializes the vw_irq_polarity.
*/
.vw_irq_polarity = ESPI_VW_IRQ_LEVEL_LOW(1) | ESPI_VW_IRQ_LEVEL_LOW(12),
}" }"
register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL" register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL"

8
src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
View File

@ -225,13 +225,7 @@ chip soc/amd/picasso
.oob_ch_en = 0, .oob_ch_en = 0,
.flash_ch_en = 0, .flash_ch_en = 0,
/* .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1) | ESPI_VW_IRQ_LEVEL_HIGH(12),
* b/160595155 - These should really be ESPI_VW_IRQ_LEVEL_HIGH,
* but eSPI gets configured in verstage which is in RO.
* We have already locked RO for zork devices so we need
* make it so x86 coreboot re-initializes the vw_irq_polarity.
*/
.vw_irq_polarity = ESPI_VW_IRQ_LEVEL_LOW(1) | ESPI_VW_IRQ_LEVEL_LOW(12),
}" }"
register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL" register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL"

1
src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h
View File

@ -63,6 +63,7 @@
#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ #define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ #define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ #define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
#define SIO_EC_PS2K_IRQ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {1}
/* /*
* Enable EC sync interrupt via GPIO controller, EC_SYNC_IRQ is defined in * Enable EC sync interrupt via GPIO controller, EC_SYNC_IRQ is defined in

1
src/mainboard/google/zork/variants/morphius/include/variant/ec.h
View File

@ -4,6 +4,7 @@
/* Enable PS/2 Mouse */ /* Enable PS/2 Mouse */
#define SIO_EC_ENABLE_PS2M #define SIO_EC_ENABLE_PS2M
#define SIO_EC_PS2M_IRQ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {12}
/* Enable DPTC support */ /* Enable DPTC support */
#define EC_ENABLE_AMD_DPTC_SUPPORT #define EC_ENABLE_AMD_DPTC_SUPPORT