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mb/google/jecht: Disable PCIe AER 

Ethernet hardware on jecht variants doesn't support AER, so
disable it to mitigate continuous AER timeout errors in dmesg:

> pcieport 0000:00:1c.0: AER: Corrected error received: 0000:00:1c.0
> pcieport 0000:00:1c.0: AER: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID)
> pcieport 0000:00:1c.0: AER: device [8086:9c94] error status/mask=00001000/00002000
> pcieport 0000:00:1c.0: AER: [12] Timeout

Change-Id: Ieda82c6e13c2bbc4b3a051a3d2a7ae90728ccdc6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46137
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Matt DeVillier 2020-10-07 13:27:55 -05:00 committed by Patrick Georgi
parent 89d5c2b6e4
commit 30f583264d
1 changed files with 3 additions and 0 deletions
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3
src/mainboard/google/jecht/Kconfig
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@ -56,4 +56,7 @@ config MAINBOARD_SMBIOS_MANUFACTURER
string
default "GOOGLE"
config PCIEXP_AER
def_bool n
endif