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pistachio: increase size of bootblock to 18 KB 

With the added code for clock and MFIOs setup, bootblock
now exceeds 16KB. This patch increases the allowed limit
to 18KB.

BUG=chrome-os-partner:31438
TEST=tested on Pistachio bring up board; works as expected
BRANCH=none

Change-Id: I166f882bd3db446bcd6f9e1f828cab22266c6ac7
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: da95db5ed348419b7905dc1ab68fd64d7b2eb5e0
Original-Change-Id: I0cacc6163f21ae3673c2716b12dde66bd48290f9
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/243213
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9665
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Ionela Voinescu 2015-01-26 13:29:34 +00:00 committed by Patrick Georgi
parent 55b8dc02e0
commit 30fc6676db
1 changed files with 3 additions and 3 deletions
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6
src/soc/imgtec/pistachio/include/soc/memlayout.ld
View File

@ -28,9 +28,9 @@ SECTIONS
/* GRAM becomes the SRAM. */ /* GRAM becomes the SRAM. */
SRAM_START(0x9a000000) SRAM_START(0x9a000000)
BOOTBLOCK(0x9a000000, 16K) BOOTBLOCK(0x9a000000, 18K)
ROMSTAGE(0x9a004000, 36K) ROMSTAGE(0x9a004800, 36K)
CBFS_CACHE(0x9a00d000, 76K) CBFS_CACHE(0x9a00d800, 74K)
SRAM_END(0x9a020000) SRAM_END(0x9a020000)
/* Let's use SRAM for stack and CBMEM console. */ /* Let's use SRAM for stack and CBMEM console. */