diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index f4273407a8..48de0c15ff 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -80,15 +80,18 @@ config CPU_SPECIFIC_OPTIONS
 	select CPU_INTEL_COMMON
 	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
 	select CPU_SUPPORTS_PM_TIMER_EMULATION
+	select DISPLAY_FSP_VERSION_INFO
 	select FSP_COMPRESS_FSP_S_LZMA
 	select FSP_M_XIP
 	select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
+	select FSP_T_XIP if FSP_CAR
 	select GENERIC_GPIO_LIB
 	select HAVE_FSP_GOP
 	select HAVE_FSP_LOGO_SUPPORT
-	select INTEL_DESCRIPTOR_MODE_CAPABLE
 	select HAVE_SMI_HANDLER
+	select HECI_DISABLE_USING_SMM if !SOC_INTEL_COFFEELAKE && !SOC_INTEL_WHISKEYLAKE && !SOC_INTEL_COMETLAKE
 	select IDT_IN_EVERY_STAGE
+	select INTEL_DESCRIPTOR_MODE_CAPABLE
 	select INTEL_GMA_ACPI
 	select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
 	select IOAPIC
@@ -96,9 +99,9 @@ config CPU_SPECIFIC_OPTIONS
 	select PARALLEL_MP
 	select PARALLEL_MP_AP_WORK
 	select PLATFORM_USES_FSP2_0
-	select REG_SCRIPT
 	select PM_ACPI_TIMER_OPTIONAL
 	select PMC_GLOBAL_RESET_ENABLE_LOCK
+	select REG_SCRIPT
 	select SOC_INTEL_COMMON
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
 	select SOC_INTEL_COMMON_BLOCK
@@ -111,26 +114,23 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
 	select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
 	select SOC_INTEL_COMMON_BLOCK_HDA
+	select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
 	select SOC_INTEL_COMMON_BLOCK_SA
 	select SOC_INTEL_COMMON_BLOCK_SCS
-	select SOC_INTEL_COMMON_BLOCK_XHCI
-	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_BLOCK_SMM
 	select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
 	select SOC_INTEL_COMMON_BLOCK_THERMAL
-	select SOC_INTEL_COMMON_PCH_BASE
-	select SOC_INTEL_COMMON_NHLT
-	select SOC_INTEL_COMMON_RESET
-	select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
+	select SOC_INTEL_COMMON_BLOCK_XHCI
+	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FSP_RESET
+	select SOC_INTEL_COMMON_NHLT
+	select SOC_INTEL_COMMON_PCH_BASE
+	select SOC_INTEL_COMMON_RESET
 	select SSE2
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select TSC_MONOTONIC_TIMER
 	select UDELAY_TSC
 	select UDK_2017_BINDING
-	select DISPLAY_FSP_VERSION_INFO
-	select FSP_T_XIP if FSP_CAR
-	select HECI_DISABLE_USING_SMM if !SOC_INTEL_COFFEELAKE && !SOC_INTEL_WHISKEYLAKE && !SOC_INTEL_COMETLAKE
 
 config MAX_CPUS
 	int