add the btest mainboard
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2459 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
parent
0a3f60775b
commit
31101c9201
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##
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## Compute the location and size of where this firmware image
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## (linuxBIOS plus bootloader) will live in the boot rom chip.
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##
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if USE_FALLBACK_IMAGE
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default ROM_SECTION_SIZE = FALLBACK_SIZE
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default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
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else
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default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
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default ROM_SECTION_OFFSET = 0
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end
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##
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## Compute the start location and size size of
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## The linuxBIOS bootloader.
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##
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default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
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##
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## Compute where this copy of linuxBIOS will start in the boot rom
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##
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default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
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##
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## Compute a range of ROM that can cached to speed up linuxBIOS,
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## execution speed.
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##
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## XIP_ROM_SIZE must be a power of 2.
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## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
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##
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default XIP_ROM_SIZE=65536
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default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
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##
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## Set all of the defaults for an x86 architecture
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##
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arch i386 end
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##
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## Build the objects we have code for in this directory.
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##
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driver mainboard.o
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if HAVE_PIRQ_TABLE object irq_tables.o end
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#object reset.o
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##
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## Romcc output
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##
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makerule ./failover.E
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depends "$(MAINBOARD)/failover.c ./romcc"
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action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
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end
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makerule ./failover.inc
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depends "$(MAINBOARD)/failover.c ./romcc"
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action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
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end
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makerule ./auto.E
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depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
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action "./romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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makerule ./auto.inc
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depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
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action "./romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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##
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## Build our 16 bit and 32 bit linuxBIOS entry code
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##
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mainboardinit cpu/x86/16bit/entry16.inc
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mainboardinit cpu/x86/32bit/entry32.inc
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ldscript /cpu/x86/16bit/entry16.lds
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ldscript /cpu/x86/32bit/entry32.lds
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##
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## Build our reset vector (This is where linuxBIOS is entered)
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##
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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### Should this be in the northbridge code?
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mainboardinit arch/i386/lib/cpu_reset.inc
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##
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## Include an id string (For safe flashing)
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##
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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###
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### This is the early phase of linuxBIOS startup
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### Things are delicate and we test to see if we should
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### failover to another image.
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###
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if USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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mainboardinit ./failover.inc
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end
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###
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### O.k. We aren't just an intermediary anymore!
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###
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##
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## Setup RAM
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##
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mainboardinit cpu/x86/fpu/enable_fpu.inc
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mainboardinit ./auto.inc
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##
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## Include the secondary Configuration files
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##
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dir /pc80
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config chip.h
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chip northbridge/amd/gx2
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register "irqmap" = "0xaa5b"
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register "setupflash" = "0"
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device apic_cluster 0 on
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chip cpu/amd/model_gx2
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device apic 0 on end
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end
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end
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device pci_domain 0 on
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device pci 1.0 on end
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device pci 1.1 on end
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chip southbridge/amd/cs5536
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# 0x51400025 (IRQ Mapper LPC Mask)= 0x00001002
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# IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
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# 0x5140004E (LPC Serial IRQ Control) = 0xEFFD0080.
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# Frame Pulse Width = 4clocks
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# IRQ Data Frames = 17Frames
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# SIRQ Mode = continous , It would be better if the EC could operate in
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# Active(Quiet) mode. Save power....
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# SIRQ Enable = Enabled
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# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
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register "lpc_irq" = "0x00001002"
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register "lpc_serirq_enable" = "0xEFFD0080"
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register "enable_gpio0_inta" = "1"
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register "enable_ide_nand_flash" = "1"
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register "enable_uarta" = "1"
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register "enable_USBP4_host" = "1"
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register "audio_irq" = "5"
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register "usbf4_irq" = "10"
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register "usbf5_irq" = "10"
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register "usbf6_irq" = "0"
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register "usbf7_irq" = "0"
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device pci d.0 on end # Realtek 8139 LAN
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device pci f.0 on end # ISA Bridge
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device pci f.2 on end # IDE Controller
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device pci f.3 on end # Audio
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device pci f.4 on end # OHCI
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device pci f.5 on end # EHCI
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register "unwanted_vpci[0]" = "0x80007E00" # USB/UDC
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register "unwanted_vpci[1]" = "0x80007F00" # USB/OTG
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register "unwanted_vpci[2]" = "0" # End of list has a zero
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end
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end
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end
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@ -0,0 +1,163 @@
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uses HAVE_MP_TABLE
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uses HAVE_PIRQ_TABLE
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uses USE_FALLBACK_IMAGE
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uses HAVE_FALLBACK_BOOT
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uses HAVE_HARD_RESET
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uses HAVE_OPTION_TABLE
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uses USE_OPTION_TABLE
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uses CONFIG_ROM_STREAM
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uses IRQ_SLOT_COUNT
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uses MAINBOARD
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uses MAINBOARD_VENDOR
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uses MAINBOARD_PART_NUMBER
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uses LINUXBIOS_EXTRA_VERSION
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uses ARCH
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uses FALLBACK_SIZE
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uses STACK_SIZE
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uses HEAP_SIZE
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uses ROM_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_IMAGE_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_SECTION_OFFSET
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uses CONFIG_ROM_STREAM_START
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uses CONFIG_COMPRESSED_ROM_STREAM_NRV2B
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uses CONFIG_COMPRESSED_ROM_STREAM_LZMA
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uses CONFIG_PRECOMPRESSED_ROM_STREAM
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uses PAYLOAD_SIZE
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uses _ROMBASE
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uses _RAMBASE
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uses XIP_ROM_SIZE
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uses XIP_ROM_BASE
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uses HAVE_MP_TABLE
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uses CROSS_COMPILE
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uses CC
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uses HOSTCC
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uses OBJCOPY
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uses DEFAULT_CONSOLE_LOGLEVEL
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uses MAXIMUM_CONSOLE_LOGLEVEL
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uses CONFIG_CONSOLE_SERIAL8250
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uses TTYS0_BAUD
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uses TTYS0_BASE
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uses TTYS0_LCS
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uses CONFIG_UDELAY_TSC
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uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
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## ROM_SIZE is the size of boot ROM that this board will use.
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default ROM_SIZE = 256*1024
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###
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### Build options
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###
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##
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## Build code for the fallback boot
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##
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default HAVE_FALLBACK_BOOT=1
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##
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## no MP table
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##
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default HAVE_MP_TABLE=0
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##
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## Build code to reset the motherboard from linuxBIOS
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##
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default HAVE_HARD_RESET=0
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## Delay timer options
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##
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default CONFIG_UDELAY_TSC=1
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default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
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##
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## Build code to export a programmable irq routing table
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##
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default HAVE_PIRQ_TABLE=1
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default IRQ_SLOT_COUNT=2
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#object irq_tables.o
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##
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## Build code to export a CMOS option table
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##
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default HAVE_OPTION_TABLE=0
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###
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### LinuxBIOS layout values
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###
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## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
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default ROM_IMAGE_SIZE = 65536
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default FALLBACK_SIZE = 131072
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##
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## Use a small 8K stack
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##
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default STACK_SIZE=0x2000
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##
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## Use a small 16K heap
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##
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default HEAP_SIZE=0x4000
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##
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## Only use the option table in a normal image
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##
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#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
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default USE_OPTION_TABLE = 0
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default _RAMBASE = 0x00004000
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default CONFIG_ROM_STREAM = 1
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##
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## The default compiler
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##
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default CROSS_COMPILE=""
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default CC="$(CROSS_COMPILE)gcc -m32"
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default HOSTCC="gcc"
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##
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## The Serial Console
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##
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# To Enable the Serial Console
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default CONFIG_CONSOLE_SERIAL8250=1
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## Select the serial console baud rate
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default TTYS0_BAUD=115200
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#default TTYS0_BAUD=57600
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#default TTYS0_BAUD=38400
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#default TTYS0_BAUD=19200
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#default TTYS0_BAUD=9600
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#default TTYS0_BAUD=4800
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#default TTYS0_BAUD=2400
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#default TTYS0_BAUD=1200
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# Select the serial console base port
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default TTYS0_BASE=0x3f8
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# Select the serial protocol
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# This defaults to 8 data bits, 1 stop bit, and no parity
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default TTYS0_LCS=0x3
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##
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### Select the linuxBIOS loglevel
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##
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## EMERG 1 system is unusable
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## ALERT 2 action must be taken immediately
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## CRIT 3 critical conditions
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## ERR 4 error conditions
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## WARNING 5 warning conditions
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## NOTICE 6 normal but significant condition
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## INFO 7 informational
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## DEBUG 8 debug-level messages
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## SPEW 9 Way too many details
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## Request this level of debugging output
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default DEFAULT_CONSOLE_LOGLEVEL=8
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## At a maximum only compile in this level of debugging
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default MAXIMUM_CONSOLE_LOGLEVEL=8
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end
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@ -0,0 +1,193 @@
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#define ASSEMBLY 1
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <arch/romcc_io.h>
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#include <arch/hlt.h>
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
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#include "cpu/x86/bist.h"
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#include "cpu/x86/msr.h"
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#include <cpu/amd/gx2def.h>
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#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
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#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
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#include "southbridge/amd/cs5536/cs5536_early_setup.c"
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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return smbus_read_byte(device, address);
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}
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#include "northbridge/amd/gx2/raminit.h"
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static inline unsigned int fls(unsigned int x)
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{
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int r;
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__asm__("bsfl %1,%0\n\t"
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"jnz 1f\n\t"
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"movl $32,%0\n"
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"1:" : "=r" (r) : "g" (x));
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return r;
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}
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/* sdram parameters for OLPC:
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row address = 13
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col address = 9
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banks = 4
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dimm0size=128MB
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d0_MB=1 (module banks)
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d0_cb=4 (component banks)
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do_psz=4KB (page size)
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Trc=10 (clocks) (ref2act)
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Tras=7 (act2pre)
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Trcd=3 (act2cmd)
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Trp=3 (pre2act)
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Trrd=2 (act2act)
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Tref=17.8ms
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*/
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static void sdram_set_spd_registers(const struct mem_controller *ctrl)
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{
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/* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) *
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* component Banks (byte 17) * module banks, side (byte 5) *
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* width in bits (byte 6,7)
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* = Density per side (byte 31) * number of sides (byte 5) */
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/* 1. Initialize GLMC registers base on SPD values, do one DIMM for now */
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msr_t msr;
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unsigned char module_banks, val;
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msr = rdmsr(MC_CF07_DATA);
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/* get module banks (sides) per dimm, SPD byte 5 */
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module_banks = 1;
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module_banks >>= 1;
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msr.hi &= ~(1 << CF07_UPPER_D0_MB_SHIFT);
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msr.hi |= (module_banks << CF07_UPPER_D0_MB_SHIFT);
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/* get component banks per module bank, SPD byte 17 */
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val = 4;
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val >>= 2;
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msr.hi &= ~(0x1 << CF07_UPPER_D0_CB_SHIFT);
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msr.hi |= (val << CF07_UPPER_D0_CB_SHIFT);
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/* get the module bank density, SPD byte 31 */
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/* this is multiples of 8 MB */
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/* actually it is 2^x*4, where x is the value you put in */
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/* for OLPC, set default size */
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/* dimm size - hardcoded 128Mb */
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val = 5;
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msr.hi &= ~(0xf << CF07_UPPER_D0_SZ_SHIFT);
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msr.hi |= (val << CF07_UPPER_D0_SZ_SHIFT);
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/* page size = 2^col address */
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val = 2; /* 4096 bytes */
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msr.hi &= ~(0x7 << CF07_UPPER_D0_PSZ_SHIFT);
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msr.hi |= (val << CF07_UPPER_D0_PSZ_SHIFT);
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print_debug("computed msr.hi ");
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print_debug_hex32(msr.hi);
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print_debug("\r\n");
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/* this is a standard value, DOES NOT PROBABLY MATCH FROM ABOVE */
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/* well, it may be close. It's about 200,000 ticks */
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msr.lo = 0x00003000;
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wrmsr(MC_CF07_DATA, msr);
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/* timing and mode ... */
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msr = rdmsr(0x20000019);
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/* per standard bios settings */
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msr.hi = 0x18000108;
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msr.lo =
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(6<<28) | // cas_lat
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(10<<24)| // ref2act
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(7<<20)| // act2pre
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(3<<16)| // pre2act
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(3<<12)| // act2cmd
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(2<<8)| // act2act
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(2<<6)| // dplwr
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(2<<4)| // dplrd
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(3); // dal
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/* the msr value reported by quanta is very, very different.
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* we will go with that value for now.
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*/
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msr.lo = 0x286332a3;
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wrmsr(0x20000019, msr);
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}
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#include "northbridge/amd/gx2/raminit.c"
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#include "sdram/generic_sdram.c"
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#define PLLMSRhi 0x00001490
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#define PLLMSRlo 0x02000030
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#define PLLMSRlo1 ((0xde << 16) | (1 << 26) | (1 << 24))
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#define PLLMSRlo2 ((1<<14) |(1<<13) | (1<<0))
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#include "northbridge/amd/gx2/pll_reset.c"
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#include "cpu/amd/model_gx2/cpureginit.c"
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#include "cpu/amd/model_gx2/syspreinit.c"
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static void msr_init(void)
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{
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__builtin_wrmsr(0x1808, 0x10f3bf00, 0x22fffc02);
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||||
__builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
|
||||
__builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
|
||||
|
||||
__builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
|
||||
__builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
|
||||
}
|
||||
|
||||
static void gpio_init(void)
|
||||
{
|
||||
unsigned long m;
|
||||
|
||||
/* Make sure events enable for gpio 12 is off */
|
||||
|
||||
m = inl(GPIOL_EVENTS_ENABLE);
|
||||
m &= ~GPIOL_12_SET;
|
||||
m |= GPIOL_12_CLEAR;
|
||||
outl(m, GPIOL_EVENTS_ENABLE);
|
||||
}
|
||||
|
||||
static void main(unsigned long bist)
|
||||
{
|
||||
static const struct mem_controller memctrl [] = {
|
||||
{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
|
||||
};
|
||||
|
||||
SystemPreInit();
|
||||
msr_init();
|
||||
|
||||
cs5536_early_setup();
|
||||
|
||||
/* NOTE: must do this AFTER the early_setup!
|
||||
* it is counting on some early MSR setup
|
||||
* for cs5536
|
||||
*/
|
||||
cs5536_setup_onchipuart();
|
||||
gpio_init();
|
||||
uart_init();
|
||||
console_init();
|
||||
|
||||
pll_reset();
|
||||
|
||||
cpuRegInit();
|
||||
print_err("done cpuRegInit\n");
|
||||
|
||||
sdram_initialize(1, memctrl);
|
||||
|
||||
/* Check all of memory */
|
||||
//ram_check(0x00000000, 640*1024);
|
||||
}
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
extern struct chip_operations mainboard_olpc_btest_ops;
|
||||
|
||||
struct mainboard_olpc_btest_config {
|
||||
int nothing;
|
||||
};
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
entries
|
||||
|
||||
#start-bit length config config-ID name
|
||||
#0 8 r 0 seconds
|
||||
#8 8 r 0 alarm_seconds
|
||||
#16 8 r 0 minutes
|
||||
#24 8 r 0 alarm_minutes
|
||||
#32 8 r 0 hours
|
||||
#40 8 r 0 alarm_hours
|
||||
#48 8 r 0 day_of_week
|
||||
#56 8 r 0 day_of_month
|
||||
#64 8 r 0 month
|
||||
#72 8 r 0 year
|
||||
#80 4 r 0 rate_select
|
||||
#84 3 r 0 REF_Clock
|
||||
#87 1 r 0 UIP
|
||||
#88 1 r 0 auto_switch_DST
|
||||
#89 1 r 0 24_hour_mode
|
||||
#90 1 r 0 binary_values_enable
|
||||
#91 1 r 0 square-wave_out_enable
|
||||
#92 1 r 0 update_finished_enable
|
||||
#93 1 r 0 alarm_interrupt_enable
|
||||
#94 1 r 0 periodic_interrupt_enable
|
||||
#95 1 r 0 disable_clock_updates
|
||||
#96 288 r 0 temporary_filler
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
385 1 e 4 last_boot
|
||||
386 1 e 1 ECC_memory
|
||||
388 4 r 0 reboot_bits
|
||||
392 3 e 5 baud_rate
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
416 4 e 7 boot_first
|
||||
420 4 e 7 boot_second
|
||||
424 4 e 7 boot_third
|
||||
428 4 h 0 boot_index
|
||||
432 8 h 0 boot_countdown
|
||||
440 1 e 0 dcon_present
|
||||
1008 16 h 0 check_sum
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
5 0 115200
|
||||
5 1 57600
|
||||
5 2 38400
|
||||
5 3 19200
|
||||
5 4 9600
|
||||
5 5 4800
|
||||
5 6 2400
|
||||
5 7 1200
|
||||
6 6 Notice
|
||||
6 7 Info
|
||||
6 8 Debug
|
||||
6 9 Spew
|
||||
7 0 Network
|
||||
7 1 HDD
|
||||
7 2 Floppy
|
||||
7 8 Fallback_Network
|
||||
7 9 Fallback_HDD
|
||||
7 10 Fallback_Floppy
|
||||
#7 3 ROM
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 1007 1008
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
|
||||
static void print_debug_pci_dev(unsigned dev)
|
||||
{
|
||||
print_debug("PCI: ");
|
||||
print_debug_hex8((dev >> 16) & 0xff);
|
||||
print_debug_char(':');
|
||||
print_debug_hex8((dev >> 11) & 0x1f);
|
||||
print_debug_char('.');
|
||||
print_debug_hex8((dev >> 8) & 7);
|
||||
}
|
||||
|
||||
static void print_pci_devices(void)
|
||||
{
|
||||
device_t dev;
|
||||
for(dev = PCI_DEV(0, 0, 0);
|
||||
dev <= PCI_DEV(0, 0x1f, 0x7);
|
||||
dev += PCI_DEV(0,0,1)) {
|
||||
uint32_t id;
|
||||
id = pci_read_config32(dev, PCI_VENDOR_ID);
|
||||
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
|
||||
(((id >> 16) & 0xffff) == 0xffff) ||
|
||||
(((id >> 16) & 0xffff) == 0x0000)) {
|
||||
continue;
|
||||
}
|
||||
print_debug_pci_dev(dev);
|
||||
print_debug("\r\n");
|
||||
}
|
||||
}
|
||||
|
||||
static void dump_pci_device(unsigned dev)
|
||||
{
|
||||
int i;
|
||||
print_debug_pci_dev(dev);
|
||||
print_debug("\r\n");
|
||||
|
||||
for(i = 0; i <= 255; i++) {
|
||||
unsigned char val;
|
||||
if ((i & 0x0f) == 0) {
|
||||
print_debug_hex8(i);
|
||||
print_debug_char(':');
|
||||
}
|
||||
val = pci_read_config8(dev, i);
|
||||
print_debug_char(' ');
|
||||
print_debug_hex8(val);
|
||||
if ((i & 0x0f) == 0x0f) {
|
||||
print_debug("\r\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void dump_pci_devices(void)
|
||||
{
|
||||
device_t dev;
|
||||
for(dev = PCI_DEV(0, 0, 0);
|
||||
dev <= PCI_DEV(0, 0x1f, 0x7);
|
||||
dev += PCI_DEV(0,0,1)) {
|
||||
uint32_t id;
|
||||
id = pci_read_config32(dev, PCI_VENDOR_ID);
|
||||
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
|
||||
(((id >> 16) & 0xffff) == 0xffff) ||
|
||||
(((id >> 16) & 0xffff) == 0x0000)) {
|
||||
continue;
|
||||
}
|
||||
dump_pci_device(dev);
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
#define ASSEMBLY 1
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <arch/io.h>
|
||||
#include "arch/romcc_io.h"
|
||||
#include "pc80/mc146818rtc_early.c"
|
||||
|
||||
static unsigned long main(unsigned long bist)
|
||||
{
|
||||
#if 0
|
||||
/* This is the primary cpu how should I boot? */
|
||||
if (do_normal_boot()) {
|
||||
goto normal_image;
|
||||
}
|
||||
else {
|
||||
goto fallback_image;
|
||||
}
|
||||
normal_image:
|
||||
asm volatile ("jmp __normal_image"
|
||||
: /* outputs */
|
||||
: "a" (bist) /* inputs */
|
||||
: /* clobbers */
|
||||
);
|
||||
cpu_reset:
|
||||
asm volatile ("jmp __cpu_reset"
|
||||
: /* outputs */
|
||||
: "a"(bist) /* inputs */
|
||||
: /* clobbers */
|
||||
);
|
||||
fallback_image:
|
||||
#endif
|
||||
return bist;
|
||||
}
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
/* This file was generated by getpir.c, do not modify!
|
||||
(but if you do, please run checkpir on it to verify)
|
||||
* Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up
|
||||
*
|
||||
* Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
|
||||
*/
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32+16*2, /* there can be total 2 devices on the bus */
|
||||
0x00, /* Where the interrupt router lies (bus) */
|
||||
(0x12<<3)|0x0, /* Where the interrupt router lies (dev) */
|
||||
0x800, /* IRQs devoted exclusively to PCI usage */
|
||||
0x1078, /* Vendor */
|
||||
0x2, /* Device */
|
||||
0, /* Crap (miniport) */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0xdf, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
||||
{
|
||||
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||
{0x00,(0x0e<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0},
|
||||
{0x00,(0x0f<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0},
|
||||
}
|
||||
};
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr);
|
||||
}
|
||||
|
|
@ -0,0 +1,109 @@
|
|||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <arch/io.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include "chip.h"
|
||||
#include "../southbridge/amd/cs5536/cs5536_smbus2.h"
|
||||
|
||||
/* Borrowed from mc146818rtc.c */
|
||||
|
||||
#define CMOS_READ(addr) ({ \
|
||||
outb((addr),RTC_PORT(0)); \
|
||||
inb(RTC_PORT(1)); \
|
||||
})
|
||||
|
||||
#define CMOS_WRITE(val, addr) ({ \
|
||||
outb((addr),RTC_PORT(0)); \
|
||||
outb((val),RTC_PORT(1)); \
|
||||
})
|
||||
|
||||
static void write_bit(unsigned char val) {
|
||||
|
||||
unsigned char byte = CMOS_READ(440 / 8);
|
||||
|
||||
/* Don't change it if its already set */
|
||||
|
||||
if ((byte & 1) == (val & 1))
|
||||
return;
|
||||
|
||||
byte &= ~1;
|
||||
byte |= val & 1;
|
||||
CMOS_WRITE(val, 440/8);
|
||||
}
|
||||
|
||||
static unsigned short _getsmbusbase(void) {
|
||||
unsigned devfn = PCI_DEVFN(0xf, 0);
|
||||
device_t dev = dev_find_slot(0x0, devfn);
|
||||
unsigned long addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
|
||||
|
||||
return (unsigned short) (addr & ~1);
|
||||
}
|
||||
|
||||
static void init_dcon(void) {
|
||||
|
||||
int ret = 1;
|
||||
unsigned short rev = 0;
|
||||
unsigned short iobase = _getsmbusbase();
|
||||
|
||||
printk_debug("CHECKING FOR DCON (%x)\n", iobase);
|
||||
|
||||
/* Get the IO base for the SMBUS */
|
||||
|
||||
rev = do_smbus_read_word(iobase, 0x0D << 1, 0x00);
|
||||
|
||||
if (rev & 0xDC00) {
|
||||
printk_debug("DCON FOUND - REV %x\n", rev);
|
||||
|
||||
/* Enable the DCON */
|
||||
ret = do_smbus_write_word(iobase, 0x0D << 1, 0x01, 0x0069);
|
||||
if (ret != 0)
|
||||
printk_debug("DCON ENABLE FAILED\n", ret);
|
||||
}
|
||||
else
|
||||
printk_debug("DCON NOT FOUND (%x)\n", rev);
|
||||
|
||||
write_bit(rev > 0 ? 1 : 0);
|
||||
}
|
||||
|
||||
static void init(struct device *dev) {
|
||||
/*
|
||||
unsigned bus = 0;
|
||||
unsigned devfn = PCI_DEVFN(0xf, 4);
|
||||
device_t usb = NULL;
|
||||
unsigned char usbirq = 0xa;
|
||||
*/
|
||||
|
||||
printk_debug("OLPC BTEST ENTER %s\n", __FUNCTION__);
|
||||
|
||||
#if 0
|
||||
/* I can't think of any reason NOT to just set this. If it turns out we want this to be
|
||||
* conditional we can make it a config variable later.
|
||||
*/
|
||||
|
||||
printk_debug("%s (%x,%x)SET USB PCI interrupt line to %d\n",
|
||||
__FUNCTION__, bus, devfn, usbirq);
|
||||
usb = dev_find_slot(bus, devfn);
|
||||
if (! usb){
|
||||
printk_err("Could not find USB\n");
|
||||
} else {
|
||||
pci_write_config8(usb, PCI_INTERRUPT_LINE, usbirq);
|
||||
}
|
||||
#endif
|
||||
|
||||
init_dcon();
|
||||
printk_debug("OLPC BTEST EXIT %s\n", __FUNCTION__);
|
||||
}
|
||||
|
||||
static void enable_dev(struct device *dev)
|
||||
{
|
||||
dev->ops->init = init;
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_olpc_btest_ops = {
|
||||
CHIP_NAME("olpc btest mainboard ")
|
||||
.enable_dev = enable_dev,
|
||||
|
||||
};
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
#if 0
|
||||
//#include "arch/romcc_io.h"
|
||||
#include <arch/io.h>
|
||||
|
||||
typedef unsigned device_t;
|
||||
|
||||
#define PCI_DEV(BUS, DEV, FN) ( \
|
||||
(((BUS) & 0xFF) << 16) | \
|
||||
(((DEV) & 0x1f) << 11) | \
|
||||
(((FN) & 0x7) << 8))
|
||||
|
||||
static void pci_write_config8(device_t dev, unsigned where, unsigned char value)
|
||||
{
|
||||
unsigned addr;
|
||||
addr = dev | where;
|
||||
outl(0x80000000 | (addr & ~3), 0xCF8);
|
||||
outb(value, 0xCFC + (addr & 3));
|
||||
}
|
||||
|
||||
static void pci_write_config32(device_t dev, unsigned where, unsigned value)
|
||||
{
|
||||
unsigned addr;
|
||||
addr = dev | where;
|
||||
outl(0x80000000 | (addr & ~3), 0xCF8);
|
||||
outl(value, 0xCFC);
|
||||
}
|
||||
|
||||
static unsigned pci_read_config32(device_t dev, unsigned where)
|
||||
{
|
||||
unsigned addr;
|
||||
addr = dev | where;
|
||||
outl(0x80000000 | (addr & ~3), 0xCF8);
|
||||
return inl(0xCFC);
|
||||
}
|
||||
|
||||
#include "../../../northbridge/amd/amdk8/reset_test.c"
|
||||
|
||||
void hard_reset(void)
|
||||
{
|
||||
set_bios_reset();
|
||||
pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1);
|
||||
}
|
||||
#endif
|
||||
Loading…
Reference in New Issue