mb/google/sarien: Enable bayhub 720 on Sarien
Add PCIe-eMMC bridge bayhub 720 on Sarien. BUG=b:157971972 BRANCH=sarien TEST=local build and boot from storage successfully Change-Id: I28f40a420d51f476487655548f386cfbdc2e5329 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Mathew King <mathewk@chromium.org>
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@ -2,6 +2,7 @@
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config BOARD_GOOGLE_BASEBOARD_SARIEN
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def_bool n
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select BOARD_ROMSIZE_KB_32768
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select DRIVERS_GENERIC_BH720
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select DRIVERS_I2C_GENERIC
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select DRIVERS_I2C_HID
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select DRIVERS_INTEL_ISH if BOARD_GOOGLE_ARCADA
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@ -2,6 +2,7 @@
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bootblock-y += bootblock.c
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ramstage-y += mainboard.c
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ramstage-y += ramstage.c
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ramstage-y += sku.c
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@ -0,0 +1,55 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <device/mmio.h>
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#include <device/pci.h>
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#include <device/pci_ops.h>
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#include <drivers/generic/bayhub/bh720.h>
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#include <string.h>
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void board_bh720(struct device *dev)
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{
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u32 sdbar;
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u32 bh720_pcr_data;
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printk(BIOS_DEBUG, "mainboard: %s init\n", __func__);
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sdbar = pci_read_config32(dev, PCI_BASE_ADDRESS_1);
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/* Enable Memory Access Function */
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write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x40000000);
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write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000000);
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write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0);
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/* Set EMMC VCCQ 1.8V PCR 0x308[4] */
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write32((void *)(sdbar + BH720_MEM_RW_ADR),
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BH720_MEM_RW_READ | BH720_PCR_EMMC_SETTING);
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bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA));
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write32((void *)(sdbar + BH720_MEM_RW_DATA),
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bh720_pcr_data | BH720_PCR_EMMC_SETTING_1_8V);
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write32((void *)(sdbar + BH720_MEM_RW_ADR),
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BH720_MEM_RW_WRITE | BH720_PCR_EMMC_SETTING);
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/* Set Base clock to 200MHz(PCR 0x304[31:16] = 0x2510) */
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write32((void *)(sdbar + BH720_MEM_RW_ADR),
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BH720_MEM_RW_READ | BH720_PCR_DrvStrength_PLL);
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bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA));
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bh720_pcr_data &= 0x0000FFFF;
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bh720_pcr_data |= 0x2510 << 16;
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write32((void *)(sdbar + BH720_MEM_RW_DATA), bh720_pcr_data);
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write32((void *)(sdbar + BH720_MEM_RW_ADR),
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BH720_MEM_RW_WRITE | BH720_PCR_DrvStrength_PLL);
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/* Use PLL Base clock PCR 0x3E4[22] = 1 */
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write32((void *)(sdbar + BH720_MEM_RW_ADR),
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BH720_MEM_RW_READ | BH720_PCR_CSR);
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bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA));
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write32((void *)(sdbar + BH720_MEM_RW_DATA),
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bh720_pcr_data | BH720_PCR_CSR_EMMC_MODE_SEL);
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write32((void *)(sdbar + BH720_MEM_RW_ADR),
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BH720_MEM_RW_WRITE | BH720_PCR_CSR);
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/* Disable Memory Access */
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write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000001);
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write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0);
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write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x80000000);
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}
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@ -395,12 +395,20 @@ chip soc/intel/cannonlake
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device pci 1c.6 off end # PCI Express Port 7
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device pci 1c.7 on end # PCI Express Port 8
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device pci 1d.0 on
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chip drivers/generic/bayhub
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register "power_saving" = "1"
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device pci 00.0 on end
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end
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smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X"
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end # PCI Express Port 9
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device pci 1d.1 on end # PCI Express Port 10
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device pci 1d.2 off end # PCI Express Port 11
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device pci 1d.3 off end # PCI Express Port 12
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device pci 1d.4 on
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chip drivers/generic/bayhub
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register "power_saving" = "1"
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device pci 00.0 on end
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end
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smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"
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end # PCI Express Port 13 (x4)
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device pci 1e.0 off end # UART #0
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