From 311ddf3b81b276553fb3a1973343b5ca31f85dbe Mon Sep 17 00:00:00 2001 From: Lean Sheng Tan Date: Fri, 1 Apr 2022 18:36:11 +0200 Subject: [PATCH] soc/intel/alderlake: Add new CPU ID Add new CPU ID 0x906A3 (L0 stepping). Signed-off-by: Lean Sheng Tan Change-Id: I280da46e5fdd3792df50556e2804b3bcb346eee3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63302 Reviewed-by: Arthur Heymans Reviewed-by: Paul Menzel Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/include/cpu/intel/cpu_ids.h | 1 + src/soc/intel/alderlake/bootblock/report_platform.c | 1 + src/soc/intel/common/block/cpu/mp_init.c | 1 + 3 files changed, 3 insertions(+) diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h index f0c1baf319..6d3685194f 100644 --- a/src/include/cpu/intel/cpu_ids.h +++ b/src/include/cpu/intel/cpu_ids.h @@ -54,6 +54,7 @@ #define CPUID_ALDERLAKE_J0 0x906a0 #define CPUID_ALDERLAKE_Q0 0x906a1 #define CPUID_ALDERLAKE_K0 0x906a2 +#define CPUID_ALDERLAKE_L0 0x906a3 #define CPUID_ALDERLAKE_R0 0x906a4 #define CPUID_ALDERLAKE_N_A0 0xb06e0 #define CPUID_METEORLAKE_A0_1 0xa06a0 diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index 721355c06a..bdce2b7b84 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -25,6 +25,7 @@ static struct { } cpu_table[] = { { CPUID_ALDERLAKE_J0, "Alderlake J0 Platform" }, { CPUID_ALDERLAKE_K0, "Alderlake K0 Platform" }, + { CPUID_ALDERLAKE_L0, "Alderlake L0 Platform" }, { CPUID_ALDERLAKE_Q0, "Alderlake Q0 Platform" }, { CPUID_ALDERLAKE_R0, "Alderlake R0 Platform" }, { CPUID_ALDERLAKE_N_A0, "Alderlake-N Platform" }, diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 0305815750..823f23edfc 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -72,6 +72,7 @@ static const struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, CPUID_ALDERLAKE_S_A0 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_J0 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_K0 }, + { X86_VENDOR_INTEL, CPUID_ALDERLAKE_L0 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_Q0 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_R0 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_N_A0 },