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soc/intel/cannonlake: Provide interface to update TCC offset 

This change provides an interface for canonlake to set TCC.
With this change, we can add code to update Tcc in devicetree.

BUG=b:122636962
TEST=Match the result from TAT UI

Change-Id: Ib54a118e4e409919e3e60112e4621a109404b16d
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
This commit is contained in:
John Su 2019-01-10 14:53:26 +08:00 committed by Patrick Georgi
parent 1d748c5346
commit 3126964d96
2 changed files with 27 additions and 0 deletions
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23
src/soc/intel/cannonlake/cpu.c
View File

@ -167,6 +167,26 @@ static void configure_c_states(void)
wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr);
}
static void configure_thermal_target(void)
{
struct device *dev = SA_DEV_ROOT;
config_t *conf = dev->chip_info;
msr_t msr;
/* Set TCC activation offset if supported */
msr = rdmsr(MSR_PLATFORM_INFO);
if ((msr.lo & (1 << 30)) && conf->tcc_offset) {
msr = rdmsr(MSR_TEMPERATURE_TARGET);
msr.lo &= ~(0xf << 24); /* Bits 27:24 */
msr.lo |= (conf->tcc_offset & 0xf) << 24;
wrmsr(MSR_TEMPERATURE_TARGET, msr);
}
msr = rdmsr(MSR_TEMPERATURE_TARGET);
msr.lo &= ~0x7f; /* Bits 6:0 */
msr.lo |= 0xe6; /* setting 100ms thermal time window */
wrmsr(MSR_TEMPERATURE_TARGET, msr);
}
/*
* The emulated ACPI timer allows replacing of the ACPI timer
* (PM1_TMR) to have no impart on the system.
@ -264,4 +284,7 @@ void soc_init_cpus(struct bus *cpu_bus)
{
if (mp_init_with_smm(cpu_bus, &mp_ops))
printk(BIOS_ERR, "MP initialization failure.\n");
/* Thermal throttle activation offset */
configure_thermal_target();
}

4
src/soc/intel/cannonlake/fsp_params.c
View File

@ -67,6 +67,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
{
int i;
FSP_S_CONFIG *params = &supd->FspsConfig;
FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig;
struct device *dev = SA_DEV_ROOT;
config_t *config = dev->chip_info;
@ -239,6 +240,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PchPmSlpSusMinAssert = config->PchPmSlpSusMinAssert;
if (config->PchPmSlpAMinAssert)
params->PchPmSlpAMinAssert = config->PchPmSlpAMinAssert;
/* Set TccActivationOffset */
tconfig->TccActivationOffset = config->tcc_offset;
}
/* Mainboard GPIO Configuration */