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src/mb/sifive/hifive-unleashed: initialize Gigabit Ethernet Controller 

Initialize the clock of the Gigabit Ethernet Controller.

Change-Id: I172dc518c9b48c122289bba5a65beece925410d4
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
This commit is contained in:
Xiang Wang 2019-01-24 14:59:58 +08:00 committed by Patrick Georgi
parent 09abb879a4
commit 313d53f6d3
1 changed files with 35 additions and 0 deletions
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35
src/soc/sifive/fu540/clock.c
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@ -59,6 +59,8 @@ static struct prci_ctlr *prci = (void *)FU540_PRCI;
#define PRCI_DDRPLLCFG1_MASK (1u << 31)
#define PRCI_GEMGXLPPLCFG1_MASK (1u << 31)
#define PRCI_CORECLKSEL_CORECLKSEL 1
#define PRCI_DEVICESRESET_DDR_CTRL_RST_N(x) (((x) & 0x1) << 0)
@ -141,6 +143,15 @@ static const struct pll_settings ddrpll_settings = {
.fse = 1,
};
static const struct pll_settings gemgxlpll_settings = {
.divr = 0,
.divf = 59,
.divq = 5,
.range = 4,
.bypass = 0,
.fse = 1,
};
static void init_coreclk(void)
{
// switch coreclk to input reference frequency before modifying PLL
@ -168,6 +179,19 @@ static void init_pll_ddr(void)
write32(&prci->ddrpllcfg1, cfg1);
}
static void init_gemgxlclk(void)
{
u32 cfg1 = read32(&prci->gemgxlpllcfg1);
clrbits_le32(&cfg1, PRCI_GEMGXLPPLCFG1_MASK);
write32(&prci->gemgxlpllcfg1, cfg1);
configure_pll(&prci->gemgxlpllcfg0, &gemgxlpll_settings);
setbits_le32(&cfg1, PRCI_GEMGXLPPLCFG1_MASK);
write32(&prci->gemgxlpllcfg1, cfg1);
}
#define FU540_UART_DEVICES 2
#define FU540_UART_REG_DIV 0x18
#define FU540_UART_DIV_VAL 4
@ -227,6 +251,17 @@ void clock_init(void)
// device?
for (int i = 0; i < 256; i++)
asm volatile ("nop");
init_gemgxlclk();
write32(&prci->devicesresetreg,
PRCI_DEVICESRESET_DDR_CTRL_RST_N(1) |
PRCI_DEVICESRESET_DDR_AXI_RST_N(1) |
PRCI_DEVICESRESET_DDR_AHB_RST_N(1) |
PRCI_DEVICESRESET_DDR_PHY_RST_N(1) |
PRCI_DEVICESRESET_GEMGXL_RST_N(1));
asm volatile ("fence");
}
#endif /* ENV_ROMSTAGE */