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Sandybridge: Set PEG clock gating 

If the PEI System Agent doesn't run PCIe initialization, the PEG
clock gating will not be setup. Add the PEG clock gating when
pei_data->pcie_init is 0.

Change-Id: I7e31bcebd11feb4807aa29b528adf09fb013c3ce
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1827
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Marc Jones 2012-11-02 14:26:44 -06:00 committed by Ronald G. Minnich
parent 7e8c8e92bb
commit 313ec9d15b
1 changed files with 8 additions and 0 deletions
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8
src/northbridge/intel/sandybridge/raminit.c
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@ -205,6 +205,13 @@ static void report_memory_config(void)
}
}
static void post_system_agent_init(struct pei_data *pei_data)
{
/* If PCIe init is skipped, set the PEG clock gating */
if (!pei_data->pcie_init)
MCHBAR32(0x7010) = MCHBAR32(0x7010) | 0x01;
}
/**
* Find PEI executable in coreboot filesystem and execute it.
*
@ -289,6 +296,7 @@ void sdram_initialize(struct pei_data *pei_data)
else
intel_early_me_status();
post_system_agent_init(pei_data);
report_memory_config();
/* S3 resume: don't save scrambler seed or MRC data */