From 314c4c3ed632c5ce090a56c484e1a2d926f54ece Mon Sep 17 00:00:00 2001 From: Kane Chen Date: Thu, 17 Jul 2014 09:51:50 -0700 Subject: [PATCH] baytrail: use the setting in devicetree.cb to config USBPHY_COMPBG USBPHY_COMPBG needs to be configured by project BUG=chrome-os-partner:30690 BRANCH=none TEST=emerge-rambi coreboot without problem checked the USBPHY_COMPBG is configured properly Original-Change-Id: I05eee384d94cf5deeec14418bd78816df0b26a92 Original-Signed-off-by: Kane Chen Original-Reviewed-on: https://chromium-review.googlesource.com/208557 Original-Reviewed-by: Shawn Nematbakhsh (cherry picked from commit 20a9c0ab7ab180596821751110f0c0a35d3ff3a1) Signed-off-by: Marc Jones Change-Id: I8bed3fa4e74e4bb4c93fa522d9df631bac2d9795 Reviewed-on: http://review.coreboot.org/8216 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/intel/baytrail/chip.h | 1 + src/soc/intel/baytrail/ehci.c | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/baytrail/chip.h b/src/soc/intel/baytrail/chip.h index f19055c1bb..97b92efb99 100644 --- a/src/soc/intel/baytrail/chip.h +++ b/src/soc/intel/baytrail/chip.h @@ -55,6 +55,7 @@ struct soc_intel_baytrail_config { uint32_t usb2_per_port_rcomp_hs_pullup2; uint32_t usb2_per_port_lane3; uint32_t usb2_per_port_rcomp_hs_pullup3; + uint32_t usb2_comp_bg; /* LPE Audio Clock configuration. */ int lpe_codec_clk_freq; /* 19 or 25 are valid. */ diff --git a/src/soc/intel/baytrail/ehci.c b/src/soc/intel/baytrail/ehci.c index 5d1a4d83c5..bfdb61aa1a 100644 --- a/src/soc/intel/baytrail/ehci.c +++ b/src/soc/intel/baytrail/ehci.c @@ -96,7 +96,8 @@ static void usb2_phy_init(device_t dev) struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script usb2_phy_script[] = { /* USB3PHYInit() */ - REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_COMPBG, 0x4700), + REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_COMPBG, + config->usb2_comp_bg), /* Per port phy settings, set in devicetree.cb */ REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE0, config->usb2_per_port_lane0),