diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h
index dc33073d3e..1d74823542 100644
--- a/src/soc/amd/common/block/include/amdblocks/lpc.h
+++ b/src/soc/amd/common/block/include/amdblocks/lpc.h
@@ -10,6 +10,8 @@
 /* PCI registers for D14F3 */
 #define LPC_PCI_CONTROL			0x40
 #define   LEGACY_DMA_EN			BIT(2)
+#define   VW_ROM_SHARING_EN		BIT(3)
+#define   EXT_ROM_SHARING_EN		BIT(4)
 
 #define LPC_IO_PORT_DECODE_ENABLE	0x44
 #define   DECODE_ENABLE_PARALLEL_PORT0	BIT(0)
@@ -148,6 +150,7 @@ void lpc_tpm_decode(void);
 void lpc_tpm_decode_spi(void);
 void lpc_enable_rom(void);
 void lpc_enable_spi_prefetch(void);
+void lpc_disable_spi_rom_sharing(void);
 
 /**
  * @brief Find the size of a particular wide IO
diff --git a/src/soc/amd/common/block/lpc/Kconfig b/src/soc/amd/common/block/lpc/Kconfig
index b0d59a55f4..3cfbfe5dcd 100644
--- a/src/soc/amd/common/block/lpc/Kconfig
+++ b/src/soc/amd/common/block/lpc/Kconfig
@@ -3,3 +3,9 @@ config SOC_AMD_COMMON_BLOCK_LPC
 	default n
 	help
 	  Select this option to use the traditional LPC-ISA bridge at D14F3.
+
+config PROVIDES_ROM_SHARING
+	bool
+	default n
+	help
+	  Select this option if the LPC bridge supports ROM sharing.
diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c
index 571c6fe8ed..45b252f99b 100644
--- a/src/soc/amd/common/block/lpc/lpc_util.c
+++ b/src/soc/amd/common/block/lpc/lpc_util.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /* This file is part of the coreboot project. */
 
+#include <assert.h>
 #include <stdint.h>
 #include <device/device.h>
 #include <device/pci_ops.h>
@@ -300,6 +301,19 @@ void lpc_enable_spi_prefetch(void)
 	pci_write_config32(_LPCB_DEV, LPC_ROM_DMA_EC_HOST_CONTROL, dword);
 }
 
+void lpc_disable_spi_rom_sharing(void)
+{
+	u8 byte;
+
+	if (!CONFIG(PROVIDES_ROM_SHARING))
+		dead_code();
+
+	byte = pci_read_config8(_LPCB_DEV, LPC_PCI_CONTROL);
+	byte &= ~VW_ROM_SHARING_EN;
+	byte &= ~EXT_ROM_SHARING_EN;
+	pci_write_config8(_LPCB_DEV, LPC_PCI_CONTROL, byte);
+}
+
 uintptr_t lpc_get_spibase(void)
 {
 	u32 base;