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Port persimmon r6591 to e350m1: ROM cache early 

Enable rom cache early to reduce boot time.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6633 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Marshall Buschman 2011-06-04 15:47:05 +00:00 committed by Peter Stuge
parent 1a7699f42a
commit 314f4a2077
2 changed files with 5 additions and 7 deletions
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7
src/mainboard/asrock/e350m1/agesawrapper.c
View File

@ -157,13 +157,6 @@ agesawrapper_amdinitmmio (
PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5;
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800;
LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
Status = AGESA_SUCCESS;
return (UINT32)Status;
}

5
src/mainboard/asrock/e350m1/romstage.c
View File

@ -47,6 +47,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 val;
u8 reg8;
// all cores: allow caching of flash chip code and data
// (there are no cache-as-ram reliability concerns with family 14h)
__writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
__writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
// all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
__writemsr (0xc0010062, 0);