fix conflich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2221 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
parent
a11e6cfd92
commit
316ea53e29
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@ -1,12 +1,21 @@
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#ifndef CPU_AMD_GX2DEF_H
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#define CPU_AMD_GX2DEF_H
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#define CPU_ID_1_X 0x540 /* Stepping ID 1.x*/
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#define CPU_ID_2_0 0x551 /* Stepping ID 2.0*/
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#define CPU_ID_2_1 0x552 /* Stepping ID 2.1*/
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#define CPU_ID_2_2 0x553 /* Stepping ID 2.2*/
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#define CPU_REV_1_0 0x011
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#define CPU_REV_1_1 0x012
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#define CPU_REV_1_2 0x013
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#define CPU_REV_1_3 0x014
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#define CPU_REV_2_0 0x020
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#define CPU_REV_2_1 0x021
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#define CPU_REV_2_2 0x022
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#define CPU_REV_3_0 0x030
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/* GeodeLink Control Processor Registers, GLIU1, Port 3 */
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#define GLCP_CLK_DIS_DELAY 0x4c000008
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#define GLCP_PMCLKDISABLE 0x4c000009
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#define GLCP_DELAY_CONTROLS 0x4c00000f
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#define GLCP_SYS_RSTPLL 0x4c000014
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#define GLCP_DOTPLL 0x4c000015
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#define GLCP_CHIP_REVID 0x4c000017
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/* GLCP_SYS_RSTPLL, Upper 32 bits */
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@ -66,14 +75,14 @@
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#define MSR_GLIU0 (GL0_GLIU0 << 29) + 1 << 28 /* To get on GeodeLink one bit has to be set */
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#define MSR_MC GL0_MC << 29
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#define MSR_GLIU1 GL0_GLIU1 << 29
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#define MSR_CPU GL0_CPU << 29 /* this is not used for BIOS since code executing on CPU doesn't need to be routed*/
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#define MSR_VG GL0_VG << 29
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#define MSR_GP GL0_GP << 29
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#define MSR_DF GL0_DF << 29
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#define MSR_MC (GL0_MC << 29)
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#define MSR_GLIU1 (GL0_GLIU1 << 29)
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#define MSR_CPU (GL0_CPU << 29) /* this is not used for BIOS since code executing on CPU doesn't need to be routed*/
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#define MSR_VG (GL0_VG << 29)
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#define MSR_GP (GL0_GP << 29)
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#define MSR_DF (GL0_DF << 29)
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#define MSR_GLCP (GL1_GLCP << 26) + MSR_GLIU1
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#define MSR_GLCP (GL1_GLCP << 26) + MSR_GLIU1
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#define MSR_PCI (GL1_PCI << 26) + MSR_GLIU1
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#define MSR_FG (GL1_FG << 26) + MSR_GLIU1
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@ -86,21 +95,21 @@
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/*GeodeLink Interface Unit 0 (GLIU0) port0*/
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/**/
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#define GLIU0_GLD_MSR_CAP MSR_GLIU0 + 2000h
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#define GLIU0_GLD_MSR_PM MSR_GLIU0 + 2004h
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#define GLIU0_GLD_MSR_CAP MSR_GLIU0 + 0x2000
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#define GLIU0_GLD_MSR_PM MSR_GLIU0 + 0x2004
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#define GLIU0_DESC_BASE MSR_GLIU0 + 20h
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#define GLIU0_CAP MSR_GLIU0 + 86h
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#define GLIU0_GLD_MSR_COH MSR_GLIU0 + 80h
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#define GLIU0_DESC_BASE MSR_GLIU0 + 0x20
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#define GLIU0_CAP MSR_GLIU0 + 0x86
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#define GLIU0_GLD_MSR_COH MSR_GLIU0 + 0x80
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/**/
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/* Memory Controller GLIU0 port 1*/
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/**/
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#define MC_GLD_MSR_CAP MSR_MC + 2000h
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#define MC_GLD_MSR_PM MSR_MC + 2004h
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#define MC_GLD_MSR_CAP MSR_MC + 0x2000
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#define MC_GLD_MSR_PM MSR_MC + 0x2004
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#define MC_CF07_DATA MSR_MC + 18h
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#define MC_CF07_DATA MSR_MC + 0x18
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#define CF07_UPPER_D1_SZ_SHIFT 28
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#define CF07_UPPER_D1_MB_SHIFT 24
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@ -112,15 +121,15 @@
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#define CF07_UPPER_D0_PSZ_SHIFT 0
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#define CF07_LOWER_REF_INT_SHIFT 8
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#define CF07_LOWER_LOAD_MODE_DDR_SET 01 << 28
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#define CF07_LOWER_LOAD_MODE_DLL_RESET 01 << 27
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#define CF07_LOWER_EMR_QFC_SET 01 << 26
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#define CF07_LOWER_EMR_DRV_SET 01 << 25
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#define CF07_LOWER_REF_TEST_SET 1 << 3
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#define CF07_LOWER_PROG_DRAM_SET 1 << 0
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#define CF07_LOWER_LOAD_MODE_DDR_SET (1 << 28)
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#define CF07_LOWER_LOAD_MODE_DLL_RESET (1 << 27)
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#define CF07_LOWER_EMR_QFC_SET (1 << 26)
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#define CF07_LOWER_EMR_DRV_SET (1 << 25)
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#define CF07_LOWER_REF_TEST_SET (1 << 3)
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#define CF07_LOWER_PROG_DRAM_SET (1 << 0)
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#define MC_CF8F_DATA MSR_MC + 19h
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#define MC_CF8F_DATA MSR_MC + 0x19
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#define CF8F_UPPER_XOR_BS_SHIFT 19
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#define CF8F_UPPER_XOR_MB0_SHIFT 18
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@ -191,19 +200,19 @@
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#define CPU_EX_BIST 1428h
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/*IM*/
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#define CPU_IM_CONFIG 1700h
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#define CPU_IM_CONFIG 0x1700
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#define IM_CONFIG_LOWER_ICD_SET 1 << 8
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#define IM_CONFIG_LOWER_QWT_SET 1 << 20
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#define CPU_IC_INDEX 1710h
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#define CPU_IC_DATA 1711h
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#define CPU_IC_TAG 1712h
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#define CPU_IC_TAG_I 1713h
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#define CPU_ITB_INDEX 1720h
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#define CPU_ITB_LRU 1721h
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#define CPU_ITB_ENTRY 1722h
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#define CPU_ITB_ENTRY_I 1723h
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#define CPU_IM_BIST_TAG 1730h
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#define CPU_IM_BIST_DATA 1731h
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#define CPU_IC_INDEX 0x1710
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#define CPU_IC_DATA 0x1711
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#define CPU_IC_TAG 0x1712
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#define CPU_IC_TAG_I 0x1713
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#define CPU_ITB_INDEX 0x1720
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#define CPU_ITB_LRU 0x1721
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#define CPU_ITB_ENTRY 0x1722
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#define CPU_ITB_ENTRY_I 0x1723
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#define CPU_IM_BIST_TAG 0x1730
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#define CPU_IM_BIST_DATA 0x1731
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/* various CPU MSRs */
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@ -292,4 +301,132 @@
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#define VG_GLD_MSR_CONFIG MSR_VG + 0x2001
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#define VG_GLD_MSR_PM MSR_VG + 0x2004
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#define GP_GLD_MSR_CAP MSR_GP + 0x2000
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#define GP_GLD_MSR_CONFIG MSR_GP + 0x2001
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#define GP_GLD_MSR_PM MSR_GP + 0x2004
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/**/
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/* DF GLIU0 port6*/
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/**/
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#define DF_GLD_MSR_CAP MSR_DF + 0x2000
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#define DF_GLD_MSR_MASTER_CONF MSR_DF + 0x2001
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#define DF_LOWER_LCD_SHIFT 6
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#define DF_GLD_MSR_PM MSR_DF + 0x2004
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/**/
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/* GeodeLink Control Processor GLIU1 port3*/
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/**/
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#define GLCP_GLD_MSR_CAP MSR_GLCP + 0x2000
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#define GLCP_GLD_MSR_CONF MSR_GLCP + 0x2001
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#define GLCP_GLD_MSR_PM MSR_GLCP + 0x2004
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#define GLCP_DELAY_CONTROLS MSR_GLCP + 0x0F
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#define GLCP_SYS_RSTPLL MSR_GLCP +0x14 /* R/W*/
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#define RSTPLL_UPPER_MDIV_SHIFT 9
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#define RSTPLL_UPPER_VDIV_SHIFT 6
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#define RSTPLL_UPPER_FBDIV_SHIFT 0
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#define RSTPLL_LOWER_SWFLAGS_SHIFT 26
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#define RSTPLL_LOWER_SWFLAGS_MASK (0x3F<<RSTPLL_LOWER_SWFLAGS_SHIFT))
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#define RSTPPL_LOWER_HOLD_COUNT_SHIFT 16
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#define RSTPPL_LOWER_BYPASS_SHIFT 15
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#define RSTPPL_LOWER_TST_SHIFT 11
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#define RSTPPL_LOWER_SDRMODE_SHIFT 10
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#define RSTPPL_LOWER_BOOTSTRAP_SHIFT 4
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#define RSTPPL_LOWER_LOCK_SET (1<<25)
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#define RSTPPL_LOWER_LOCKWAIT_SET (1<<24)
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#define RSTPPL_LOWER_BYPASS_SET (1<<15)
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#define RSTPPL_LOWER_PD_SET (1<<14)
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#define RSTPPL_LOWER_PLL_RESET_SET (1<<13)
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#define RSTPPL_LOWER_SDRMODE_SET (1<<10)
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#define RSTPPL_LOWER_CPU_SEMI_SYNC_SET (1<<9)
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#define RSTPPL_LOWER_PCI_SEMI_SYNC_SET (1<<8)
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#define RSTPPL_LOWER_CHIP_RESET_SET (1<<0)
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#define GLCP_DOTPLL MSR_GLCP + 0x15 /* R/W*/
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#define DOTPPL_LOWER_PD_SET (1<<14)
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/**/
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/* GLIU1 port 4*/
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/**/
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#define GLPCI_GLD_MSR_CAP MSR_PCI + 0x2000
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#define GLPCI_GLD_MSR_CONFIG MSR_PCI + 0x2001
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#define GLPCI_GLD_MSR_PM MSR_PCI + 0x2004
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#define GLPCI_CTRL MSR_PCI + 0x2010
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#define GLPCI_CTRL_UPPER_FTH_SHIFT 28
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#define GLPCI_CTRL_UPPER_RTH_SHIFT 24
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#define GLPCI_CTRL_UPPER_SBRTH_SHIFT 20
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#define GLPCI_CTRL_UPPER_DTL_SHIFT 14
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#define GLPCI_CTRL_UPPER_WTO_SHIFT 11
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#define GLPCI_CTRL_UPPER_LAT_SHIFT 3
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#define GLPCI_CTRL_UPPER_ILTO_SHIFT 8
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#define GLPCI_CTRL_LOWER_IRFT_SHIFT 18
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#define GLPCI_CTRL_LOWER_IRFC_SHIFT 16
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#define GLPCI_CTRL_LOWER_ER_SET (1<<11)
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#define GLPCI_CTRL_LOWER_LDE_SET (1<<9)
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#define GLPCI_CTRL_LOWER_OWC_SET (1<<4)
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#define GLPCI_CTRL_LOWER_IWC_SET (1<<3)
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#define GLPCI_CTRL_LOWER_PCD_SET (1<<2)
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#define GLPCI_CTRL_LOWER_ME_SET (1<<0)
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#define GLPCI_ARB MSR_PCI + 0x2011
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#define GLPCI_ARB_UPPER_BM1_SET (1<<17)
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#define GLPCI_ARB_UPPER_BM0_SET (1<<16)
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#define GLPCI_ARB_UPPER_CPRE_SET (1<<15)
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#define GLPCI_ARB_UPPER_PRE2_SET (1<<10)
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#define GLPCI_ARB_UPPER_PRE1_SET (1<<9)
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#define GLPCI_ARB_UPPER_PRE0_SET (1<<8)
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#define GLPCI_ARB_UPPER_CRME_SET (1<<7)
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#define GLPCI_ARB_UPPER_RME2_SET (1<<2)
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#define GLPCI_ARB_UPPER_RME1_SET (1<<1)
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#define GLPCI_ARB_UPPER_RME0_SET (1<<0)
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#define GLPCI_ARB_LOWER_PRCM_SHIFT 24
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#define GLPCI_ARB_LOWER_FPVEC_SHIFT 16
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#define GLPCI_ARB_LOWER_RMT_SHIFT 6
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#define GLPCI_ARB_LOWER_IIE_SET (1<<8)
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#define GLPCI_ARB_LOWER_PARK_SET (1<<0)
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#define GLPCI_REN MSR_PCI + 0x2014
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#define GLPCI_A0_BF MSR_PCI + 0x2015
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#define GLPCI_C0_DF MSR_PCI + 0x2016
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#define GLPCI_E0_FF MSR_PCI + 0x2017
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#define GLPCI_RC0 MSR_PCI + 0x2018
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#define GLPCI_RC1 MSR_PCI + 0x2019
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#define GLPCI_RC2 MSR_PCI + 0x201A
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#define GLPCI_RC3 MSR_PCI + 0x201B
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#define GLPCI_RC4 MSR_PCI + 0x201C
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#define GLPCI_RC_UPPER_TOP_SHIFT 12
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#define GLPCI_RC_LOWER_BASE_SHIFT 12
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#define GLPCI_RC_LOWER_EN_SET (1<<8)
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#define GLPCI_RC_LOWER_PF_SET (1<<5)
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#define GLPCI_RC_LOWER_WC_SET (1<<4)
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#define GLPCI_RC_LOWER_WP_SET (1<<2)
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#define GLPCI_RC_LOWER_CD_SET (1<<0)
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#define GLPCI_ExtMSR MSR_PCI + 0x201E
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#define GLPCI_SPARE MSR_PCI + 0x201F
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#define GLPCI_SPARE_LOWER_AILTO_SET (1<<6)
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#define GLPCI_SPARE_LOWER_PPD_SET (1<<5)
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#define GLPCI_SPARE_LOWER_PPC_SET (1<<4)
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#define GLPCI_SPARE_LOWER_MPC_SET (1<<3)
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#define GLPCI_SPARE_LOWER_MME_SET (1<<2)
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#define GLPCI_SPARE_LOWER_NSE_SET (1<<1)
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#define GLPCI_SPARE_LOWER_SUPO_SET (1<<0)
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/**/
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/* FooGlue GLIU1 port 5*/
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/**/
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#define FG_GLD_MSR_CAP MSR_FG + 0x2000
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#define FG_GLD_MSR_PM MSR_FG + 0x2004
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#endif /* CPU_AMD_GX2DEF_H */
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