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fix conflich 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2221 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich 2006-03-20 22:20:09 +00:00
parent a11e6cfd92
commit 316ea53e29
1 changed files with 173 additions and 36 deletions
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209
src/include/cpu/amd/gx2def.h
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@ -1,12 +1,21 @@
#ifndef CPU_AMD_GX2DEF_H #ifndef CPU_AMD_GX2DEF_H
#define CPU_AMD_GX2DEF_H #define CPU_AMD_GX2DEF_H
#define CPU_ID_1_X 0x540 /* Stepping ID 1.x*/
#define CPU_ID_2_0 0x551 /* Stepping ID 2.0*/
#define CPU_ID_2_1 0x552 /* Stepping ID 2.1*/
#define CPU_ID_2_2 0x553 /* Stepping ID 2.2*/
#define CPU_REV_1_0 0x011
#define CPU_REV_1_1 0x012
#define CPU_REV_1_2 0x013
#define CPU_REV_1_3 0x014
#define CPU_REV_2_0 0x020
#define CPU_REV_2_1 0x021
#define CPU_REV_2_2 0x022
#define CPU_REV_3_0 0x030
/* GeodeLink Control Processor Registers, GLIU1, Port 3 */ /* GeodeLink Control Processor Registers, GLIU1, Port 3 */
#define GLCP_CLK_DIS_DELAY 0x4c000008 #define GLCP_CLK_DIS_DELAY 0x4c000008
#define GLCP_PMCLKDISABLE 0x4c000009 #define GLCP_PMCLKDISABLE 0x4c000009
#define GLCP_DELAY_CONTROLS 0x4c00000f
#define GLCP_SYS_RSTPLL 0x4c000014
#define GLCP_DOTPLL 0x4c000015
#define GLCP_CHIP_REVID 0x4c000017 #define GLCP_CHIP_REVID 0x4c000017
/* GLCP_SYS_RSTPLL, Upper 32 bits */ /* GLCP_SYS_RSTPLL, Upper 32 bits */
@ -66,14 +75,14 @@
#define MSR_GLIU0 (GL0_GLIU0 << 29) + 1 << 28 /* To get on GeodeLink one bit has to be set */ #define MSR_GLIU0 (GL0_GLIU0 << 29) + 1 << 28 /* To get on GeodeLink one bit has to be set */
#define MSR_MC GL0_MC << 29 #define MSR_MC (GL0_MC << 29)
#define MSR_GLIU1 GL0_GLIU1 << 29 #define MSR_GLIU1 (GL0_GLIU1 << 29)
#define MSR_CPU GL0_CPU << 29 /* this is not used for BIOS since code executing on CPU doesn't need to be routed*/ #define MSR_CPU (GL0_CPU << 29) /* this is not used for BIOS since code executing on CPU doesn't need to be routed*/
#define MSR_VG GL0_VG << 29 #define MSR_VG (GL0_VG << 29)
#define MSR_GP GL0_GP << 29 #define MSR_GP (GL0_GP << 29)
#define MSR_DF GL0_DF << 29 #define MSR_DF (GL0_DF << 29)
#define MSR_GLCP (GL1_GLCP << 26) + MSR_GLIU1 #define MSR_GLCP (GL1_GLCP << 26) + MSR_GLIU1
#define MSR_PCI (GL1_PCI << 26) + MSR_GLIU1 #define MSR_PCI (GL1_PCI << 26) + MSR_GLIU1
#define MSR_FG (GL1_FG << 26) + MSR_GLIU1 #define MSR_FG (GL1_FG << 26) + MSR_GLIU1
@ -86,21 +95,21 @@
/*GeodeLink Interface Unit 0 (GLIU0) port0*/ /*GeodeLink Interface Unit 0 (GLIU0) port0*/
/**/ /**/
#define GLIU0_GLD_MSR_CAP MSR_GLIU0 + 2000h #define GLIU0_GLD_MSR_CAP MSR_GLIU0 + 0x2000
#define GLIU0_GLD_MSR_PM MSR_GLIU0 + 2004h #define GLIU0_GLD_MSR_PM MSR_GLIU0 + 0x2004
#define GLIU0_DESC_BASE MSR_GLIU0 + 20h #define GLIU0_DESC_BASE MSR_GLIU0 + 0x20
#define GLIU0_CAP MSR_GLIU0 + 86h #define GLIU0_CAP MSR_GLIU0 + 0x86
#define GLIU0_GLD_MSR_COH MSR_GLIU0 + 80h #define GLIU0_GLD_MSR_COH MSR_GLIU0 + 0x80
/**/ /**/
/* Memory Controller GLIU0 port 1*/ /* Memory Controller GLIU0 port 1*/
/**/ /**/
#define MC_GLD_MSR_CAP MSR_MC + 2000h #define MC_GLD_MSR_CAP MSR_MC + 0x2000
#define MC_GLD_MSR_PM MSR_MC + 2004h #define MC_GLD_MSR_PM MSR_MC + 0x2004
#define MC_CF07_DATA MSR_MC + 18h #define MC_CF07_DATA MSR_MC + 0x18
#define CF07_UPPER_D1_SZ_SHIFT 28 #define CF07_UPPER_D1_SZ_SHIFT 28
#define CF07_UPPER_D1_MB_SHIFT 24 #define CF07_UPPER_D1_MB_SHIFT 24
@ -112,15 +121,15 @@
#define CF07_UPPER_D0_PSZ_SHIFT 0 #define CF07_UPPER_D0_PSZ_SHIFT 0
#define CF07_LOWER_REF_INT_SHIFT 8 #define CF07_LOWER_REF_INT_SHIFT 8
#define CF07_LOWER_LOAD_MODE_DDR_SET 01 << 28 #define CF07_LOWER_LOAD_MODE_DDR_SET (1 << 28)
#define CF07_LOWER_LOAD_MODE_DLL_RESET 01 << 27 #define CF07_LOWER_LOAD_MODE_DLL_RESET (1 << 27)
#define CF07_LOWER_EMR_QFC_SET 01 << 26 #define CF07_LOWER_EMR_QFC_SET (1 << 26)
#define CF07_LOWER_EMR_DRV_SET 01 << 25 #define CF07_LOWER_EMR_DRV_SET (1 << 25)
#define CF07_LOWER_REF_TEST_SET 1 << 3 #define CF07_LOWER_REF_TEST_SET (1 << 3)
#define CF07_LOWER_PROG_DRAM_SET 1 << 0 #define CF07_LOWER_PROG_DRAM_SET (1 << 0)
#define MC_CF8F_DATA MSR_MC + 19h #define MC_CF8F_DATA MSR_MC + 0x19
#define CF8F_UPPER_XOR_BS_SHIFT 19 #define CF8F_UPPER_XOR_BS_SHIFT 19
#define CF8F_UPPER_XOR_MB0_SHIFT 18 #define CF8F_UPPER_XOR_MB0_SHIFT 18
@ -191,19 +200,19 @@
#define CPU_EX_BIST 1428h #define CPU_EX_BIST 1428h
/*IM*/ /*IM*/
#define CPU_IM_CONFIG 1700h #define CPU_IM_CONFIG 0x1700
#define IM_CONFIG_LOWER_ICD_SET 1 << 8 #define IM_CONFIG_LOWER_ICD_SET 1 << 8
#define IM_CONFIG_LOWER_QWT_SET 1 << 20 #define IM_CONFIG_LOWER_QWT_SET 1 << 20
#define CPU_IC_INDEX 1710h #define CPU_IC_INDEX 0x1710
#define CPU_IC_DATA 1711h #define CPU_IC_DATA 0x1711
#define CPU_IC_TAG 1712h #define CPU_IC_TAG 0x1712
#define CPU_IC_TAG_I 1713h #define CPU_IC_TAG_I 0x1713
#define CPU_ITB_INDEX 1720h #define CPU_ITB_INDEX 0x1720
#define CPU_ITB_LRU 1721h #define CPU_ITB_LRU 0x1721
#define CPU_ITB_ENTRY 1722h #define CPU_ITB_ENTRY 0x1722
#define CPU_ITB_ENTRY_I 1723h #define CPU_ITB_ENTRY_I 0x1723
#define CPU_IM_BIST_TAG 1730h #define CPU_IM_BIST_TAG 0x1730
#define CPU_IM_BIST_DATA 1731h #define CPU_IM_BIST_DATA 0x1731
/* various CPU MSRs */ /* various CPU MSRs */
@ -292,4 +301,132 @@
#define VG_GLD_MSR_CONFIG MSR_VG + 0x2001 #define VG_GLD_MSR_CONFIG MSR_VG + 0x2001
#define VG_GLD_MSR_PM MSR_VG + 0x2004 #define VG_GLD_MSR_PM MSR_VG + 0x2004
#define GP_GLD_MSR_CAP MSR_GP + 0x2000
#define GP_GLD_MSR_CONFIG MSR_GP + 0x2001
#define GP_GLD_MSR_PM MSR_GP + 0x2004
/**/
/* DF GLIU0 port6*/
/**/
#define DF_GLD_MSR_CAP MSR_DF + 0x2000
#define DF_GLD_MSR_MASTER_CONF MSR_DF + 0x2001
#define DF_LOWER_LCD_SHIFT 6
#define DF_GLD_MSR_PM MSR_DF + 0x2004
/**/
/* GeodeLink Control Processor GLIU1 port3*/
/**/
#define GLCP_GLD_MSR_CAP MSR_GLCP + 0x2000
#define GLCP_GLD_MSR_CONF MSR_GLCP + 0x2001
#define GLCP_GLD_MSR_PM MSR_GLCP + 0x2004
#define GLCP_DELAY_CONTROLS MSR_GLCP + 0x0F
#define GLCP_SYS_RSTPLL MSR_GLCP +0x14 /* R/W*/
#define RSTPLL_UPPER_MDIV_SHIFT 9
#define RSTPLL_UPPER_VDIV_SHIFT 6
#define RSTPLL_UPPER_FBDIV_SHIFT 0
#define RSTPLL_LOWER_SWFLAGS_SHIFT 26
#define RSTPLL_LOWER_SWFLAGS_MASK (0x3F<<RSTPLL_LOWER_SWFLAGS_SHIFT))
#define RSTPPL_LOWER_HOLD_COUNT_SHIFT 16
#define RSTPPL_LOWER_BYPASS_SHIFT 15
#define RSTPPL_LOWER_TST_SHIFT 11
#define RSTPPL_LOWER_SDRMODE_SHIFT 10
#define RSTPPL_LOWER_BOOTSTRAP_SHIFT 4
#define RSTPPL_LOWER_LOCK_SET (1<<25)
#define RSTPPL_LOWER_LOCKWAIT_SET (1<<24)
#define RSTPPL_LOWER_BYPASS_SET (1<<15)
#define RSTPPL_LOWER_PD_SET (1<<14)
#define RSTPPL_LOWER_PLL_RESET_SET (1<<13)
#define RSTPPL_LOWER_SDRMODE_SET (1<<10)
#define RSTPPL_LOWER_CPU_SEMI_SYNC_SET (1<<9)
#define RSTPPL_LOWER_PCI_SEMI_SYNC_SET (1<<8)
#define RSTPPL_LOWER_CHIP_RESET_SET (1<<0)
#define GLCP_DOTPLL MSR_GLCP + 0x15 /* R/W*/
#define DOTPPL_LOWER_PD_SET (1<<14)
/**/
/* GLIU1 port 4*/
/**/
#define GLPCI_GLD_MSR_CAP MSR_PCI + 0x2000
#define GLPCI_GLD_MSR_CONFIG MSR_PCI + 0x2001
#define GLPCI_GLD_MSR_PM MSR_PCI + 0x2004
#define GLPCI_CTRL MSR_PCI + 0x2010
#define GLPCI_CTRL_UPPER_FTH_SHIFT 28
#define GLPCI_CTRL_UPPER_RTH_SHIFT 24
#define GLPCI_CTRL_UPPER_SBRTH_SHIFT 20
#define GLPCI_CTRL_UPPER_DTL_SHIFT 14
#define GLPCI_CTRL_UPPER_WTO_SHIFT 11
#define GLPCI_CTRL_UPPER_LAT_SHIFT 3
#define GLPCI_CTRL_UPPER_ILTO_SHIFT 8
#define GLPCI_CTRL_LOWER_IRFT_SHIFT 18
#define GLPCI_CTRL_LOWER_IRFC_SHIFT 16
#define GLPCI_CTRL_LOWER_ER_SET (1<<11)
#define GLPCI_CTRL_LOWER_LDE_SET (1<<9)
#define GLPCI_CTRL_LOWER_OWC_SET (1<<4)
#define GLPCI_CTRL_LOWER_IWC_SET (1<<3)
#define GLPCI_CTRL_LOWER_PCD_SET (1<<2)
#define GLPCI_CTRL_LOWER_ME_SET (1<<0)
#define GLPCI_ARB MSR_PCI + 0x2011
#define GLPCI_ARB_UPPER_BM1_SET (1<<17)
#define GLPCI_ARB_UPPER_BM0_SET (1<<16)
#define GLPCI_ARB_UPPER_CPRE_SET (1<<15)
#define GLPCI_ARB_UPPER_PRE2_SET (1<<10)
#define GLPCI_ARB_UPPER_PRE1_SET (1<<9)
#define GLPCI_ARB_UPPER_PRE0_SET (1<<8)
#define GLPCI_ARB_UPPER_CRME_SET (1<<7)
#define GLPCI_ARB_UPPER_RME2_SET (1<<2)
#define GLPCI_ARB_UPPER_RME1_SET (1<<1)
#define GLPCI_ARB_UPPER_RME0_SET (1<<0)
#define GLPCI_ARB_LOWER_PRCM_SHIFT 24
#define GLPCI_ARB_LOWER_FPVEC_SHIFT 16
#define GLPCI_ARB_LOWER_RMT_SHIFT 6
#define GLPCI_ARB_LOWER_IIE_SET (1<<8)
#define GLPCI_ARB_LOWER_PARK_SET (1<<0)
#define GLPCI_REN MSR_PCI + 0x2014
#define GLPCI_A0_BF MSR_PCI + 0x2015
#define GLPCI_C0_DF MSR_PCI + 0x2016
#define GLPCI_E0_FF MSR_PCI + 0x2017
#define GLPCI_RC0 MSR_PCI + 0x2018
#define GLPCI_RC1 MSR_PCI + 0x2019
#define GLPCI_RC2 MSR_PCI + 0x201A
#define GLPCI_RC3 MSR_PCI + 0x201B
#define GLPCI_RC4 MSR_PCI + 0x201C
#define GLPCI_RC_UPPER_TOP_SHIFT 12
#define GLPCI_RC_LOWER_BASE_SHIFT 12
#define GLPCI_RC_LOWER_EN_SET (1<<8)
#define GLPCI_RC_LOWER_PF_SET (1<<5)
#define GLPCI_RC_LOWER_WC_SET (1<<4)
#define GLPCI_RC_LOWER_WP_SET (1<<2)
#define GLPCI_RC_LOWER_CD_SET (1<<0)
#define GLPCI_ExtMSR MSR_PCI + 0x201E
#define GLPCI_SPARE MSR_PCI + 0x201F
#define GLPCI_SPARE_LOWER_AILTO_SET (1<<6)
#define GLPCI_SPARE_LOWER_PPD_SET (1<<5)
#define GLPCI_SPARE_LOWER_PPC_SET (1<<4)
#define GLPCI_SPARE_LOWER_MPC_SET (1<<3)
#define GLPCI_SPARE_LOWER_MME_SET (1<<2)
#define GLPCI_SPARE_LOWER_NSE_SET (1<<1)
#define GLPCI_SPARE_LOWER_SUPO_SET (1<<0)
/**/
/* FooGlue GLIU1 port 5*/
/**/
#define FG_GLD_MSR_CAP MSR_FG + 0x2000
#define FG_GLD_MSR_PM MSR_FG + 0x2004
#endif /* CPU_AMD_GX2DEF_H */ #endif /* CPU_AMD_GX2DEF_H */