google/glados: fix kepler probing
On proto2 boards the kepler device has its reset line pulled up to one of its IO rails with a zener in between. This results in the device not being visible at MemoryInit() time because for some reason FSP is doing PCIE configuration/probing in that path. Hack around the broken FSP logic by configuring the pads for kepler's power and clkreq. BUG=chrome-os-partner:44326 BRANCH=None TEST=Built and booted glados. lscpi shows the device on bus 2. Change-Id: I543eb3ccd3ab5ffacd6efc959e6e2f7a88de78b3 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 67f6b57487e8724b469f74870e0083d4e1dac4d2 Original-Change-Id: I7fe4a707f9321b7bdec4b4be729c5d0dcce65f6e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294810 Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11419 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -48,6 +48,7 @@
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#define EC_SMI_GPI GPP_E15
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#define EC_SMI_GPI GPP_E15
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#ifndef __ACPI__
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#ifndef __ACPI__
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/* Pad configuration in ramstage. */
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static const struct pad_config gpio_table[] = {
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static const struct pad_config gpio_table[] = {
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/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
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/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
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/* LAD0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
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/* LAD0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
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@ -219,6 +220,13 @@ static const struct pad_config gpio_table[] = {
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/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
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/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
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/* LANPHYC */ /* GPD11 */
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/* LANPHYC */ /* GPD11 */
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};
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};
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/* Early pad configuration in romstage. */
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static const struct pad_config early_gpio_table[] = {
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/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */
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/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_KEPLER */
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};
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#endif
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#endif
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#endif
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#endif
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@ -27,10 +27,21 @@
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#include <soc/pei_data.h>
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#include <soc/pei_data.h>
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#include <soc/pei_wrapper.h>
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#include <soc/pei_wrapper.h>
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#include <soc/romstage.h>
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#include <soc/romstage.h>
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#include "gpio.h"
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#include "spd/spd.h"
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#include "spd/spd.h"
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static void early_config_gpio(void)
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{
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/* This is a hack for FSP because it does things in MemoryInit()
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* which it shouldn't be. We have to prepare certain gpios here
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* because of the brokenness in FSP. */
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gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
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}
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void mainboard_romstage_entry(struct romstage_params *params)
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void mainboard_romstage_entry(struct romstage_params *params)
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{
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{
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early_config_gpio();
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/* Fill out PEI DATA */
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/* Fill out PEI DATA */
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mainboard_fill_pei_data(params->pei_data);
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mainboard_fill_pei_data(params->pei_data);
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mainboard_fill_spd_data(params->pei_data);
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mainboard_fill_spd_data(params->pei_data);
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