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soc/intel/tigerlake: Configure Hyperthreading 

Configure Hyperthreading based on devicetree

BUG=none
TEST= Build and boot with FSP log and check Hyperthread setting

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Idc94e6b8ecd59a43be60bf60dc7dd0811ac0350b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39683
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Wonkyu Kim 2020-03-19 15:30:06 -07:00 committed by Patrick Georgi
parent 825332d3c9
commit 3180af7fd6
2 changed files with 5 additions and 2 deletions
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2
src/soc/intel/tigerlake/chip.h
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@ -292,6 +292,8 @@ struct soc_intel_tigerlake_config {
*/ */
uint8_t cpu_ratio_override; uint8_t cpu_ratio_override;
/* HyperThreadingDisable : Yes (1) / No (0) */
uint8_t HyperThreadingDisable;
}; };
typedef struct soc_intel_tigerlake_config config_t; typedef struct soc_intel_tigerlake_config config_t;

5
src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
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@ -143,8 +143,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
else else
m_cfg->TcssItbtPcie3En = 0; m_cfg->TcssItbtPcie3En = 0;
/* Enable Hyper Threading */ /* Hyper Threading */
m_cfg->HyperThreading = 1; m_cfg->HyperThreading = !config->HyperThreadingDisable;
/* Disable Lock PCU Thermal Management registers */ /* Disable Lock PCU Thermal Management registers */
m_cfg->LockPTMregs = 0; m_cfg->LockPTMregs = 0;
/* Channel Hash Mask:0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum) */ /* Channel Hash Mask:0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum) */