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AMD CIMX: Drop unused code 

We never define B1_IMAGE or B2_IMAGE. These are about building
CIMx as separate binary modules, while coreboot builds these into
same romstage or ramstage module.

Change-Id: I9cfa3f0bff8332aff4b661d56d0e7b340a992992
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14393
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
This commit is contained in:
Kyösti Mälkki 2016-04-18 14:34:18 +03:00
parent 0793afe913
commit 318e2ac974
13 changed files with 2 additions and 358 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/amd/dinar/rd890_cfg.c
View File

@ -220,7 +220,6 @@ void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CON
AmdInitializer(pConfig);
pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */
//pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS;
pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS;
pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry;

1
src/mainboard/supermicro/h8qgi/rd890_cfg.c
View File

@ -220,7 +220,6 @@ void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CON
AmdInitializer(pConfig);
pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */
//pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS;
pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS;
pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry;

1
src/mainboard/supermicro/h8scm/rd890_cfg.c
View File

@ -220,7 +220,6 @@ void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CON
AmdInitializer(pConfig);
pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */
//pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS;
pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS;
pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry;

1
src/mainboard/tyan/s8226/rd890_cfg.c
View File

@ -220,7 +220,6 @@ void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CON
AmdInitializer(pConfig);
pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */
//pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS;
pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS;
pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry;

7
src/northbridge/amd/cimx/rd890/NbPlatform.h
View File

@ -66,16 +66,9 @@
//#define STALL(Ptr, TimeUs, Flag) LibAmdSbStall(TimeUs)
#define STALL(Ptr, TimeUs, Flag) LibAmdSbStall(TimeUs, Ptr)
#ifdef B2_IMAGE
#define REPORT_EVENT(Class, Info, Param1, Param2, Param3, Param4, CfgPtr) LibNbEventLog(Class, Info, Param1, Param2, Param3, Param4, CfgPtr)
#else
#define REPORT_EVENT(Class, Info, Param1, Param2, Param3, Param4, CfgPtr)
#endif
// CIMX configuration parameters
//#define CIMX_B2_IMAGE_BASE_ADDRESS 0xFFF40000
/*
* PCIEX_BASE_ADDRESS - Define PCIE base address
*/

102
src/vendorcode/amd/cimx/rd890/nbDispatcher.c
View File

@ -85,109 +85,9 @@ AmdNbDispatcher (
CIMX_TRACE ((TRACE_DATA (ConfigPtr, CIMX_TRACE_ALL), "CIMx - RD890 Entry \n"));
CIMX_TRACE ((TRACE_DATA (ConfigPtr, CIMX_TRACE_ALL), " Funcid = %x Callout = %x\n", ((AMD_CONFIG_PARAMS*)ConfigPtr)->Func, ((AMD_CONFIG_PARAMS*)ConfigPtr)->CalloutPtr));
#ifdef B1_IMAGE
// 1. Try to execute any B1 specific functions
switch (((AMD_CONFIG_PARAMS*)ConfigPtr)->Func) {
#ifdef B1_IMAGE
// B1 ONLY Functions
//
//
#endif
default:
break;
}
#endif
// 2. If not B1 specific function but we are B1, see if we can find B2 instead
#ifdef B1_IMAGE
if (Status == AGESA_UNSUPPORTED) {
UINTN ImageStart;
UINTN ImageEnd;
AMD_IMAGE_HEADER* AltImagePtr;
ImageStart = 0xFFF00000;
ImageEnd = 0xFFFFFFFF;
AltImagePtr = (AMD_IMAGE_HEADER*) (UINTN) ((AMD_CONFIG_PARAMS*)ConfigPtr)->AltImageBasePtr;
// 2. AltImage not supported
if ((UINTN)AltImagePtr != 0xFFFFFFFF) {
if (AltImagePtr != NULL) {
ImageStart = (UINT32) (UINTN)AltImagePtr;
ImageEnd = ImageStart + 4;
}
// Locate/test image base that matches this component
AltImagePtr = LibAmdLocateImage ((VOID*)ImageStart, (VOID*)ImageEnd, 4096, CIMX_NB_ID);
if (AltImagePtr != NULL) {
//Invoke alternative Image
ImageEntry = (IMAGE_ENTRY) (UINTN) ((UINT8*) AltImagePtr + AltImagePtr->EntryPointAddress);
Status = (*ImageEntry) (ConfigPtr);
}
}
}
#endif
if (Status == AGESA_UNSUPPORTED) {
// 3. Try to execute any other functions
switch (((AMD_CONFIG_PARAMS*)ConfigPtr)->Func) {
#if defined (B1_IMAGE) || defined (B2_IMAGE)
// B1 & B2 Functions
case PH_AmdPowerOnResetInit:
Status = LibSystemApiCall (AmdPowerOnResetInit, ConfigPtr);
break;
case PH_AmdPcieEarlyInit:
Status = LibSystemApiCall (AmdPcieEarlyInit, ConfigPtr);
break;
case PH_AmdInitializer:
Status = LibSystemApiCall (AmdInitializer, ConfigPtr);
break;
#endif
#ifdef B2_IMAGE
// B2 Functions
case PH_AmdNbHtInit :
Status = LibSystemApiCall (AmdHtInit, ConfigPtr);
break;
case PH_AmdEarlyPostInit :
LibSystemApiCall (AmdMaskedMemoryInit, ConfigPtr);
Status = LibSystemApiCall (AmdEarlyPostInit, ConfigPtr);
break;
case PH_AmdMidPostInit :
Status = LibSystemApiCall (AmdMidPostInit, ConfigPtr);
break;
case PH_AmdLatePostInit :
Status = LibSystemApiCall (AmdPcieLateInit, ConfigPtr);
Status = LibSystemApiCall (AmdLatePostInit, ConfigPtr);
Status = LibSystemApiCall (AmdPcieLateInitWa, ConfigPtr);
break;
case PH_AmdPcieValidatePortState :
Status = LibSystemApiCall (AmdPcieValidatePortState, ConfigPtr);
break;
case PH_AmdPcieLateInit :
Status = LibSystemApiCall (AmdPcieLateInit, ConfigPtr);
break;
case PH_AmdNbLateInit :
Status = LibSystemApiCall (AmdLatePostInit, ConfigPtr);
break;
case PH_AmdS3Init :
LibSystemApiCall (AmdMaskedMemoryInit, ConfigPtr);
Status = LibSystemApiCall (AmdS3InitIommu, ConfigPtr);
Status = LibSystemApiCall (AmdPcieS3Init, ConfigPtr);
Status = LibSystemApiCall (AmdS3Init, ConfigPtr);
Status = LibSystemApiCall (AmdPcieLateInitWa, ConfigPtr);
break;
case PH_AmdNbS3Init :
LibSystemApiCall (AmdMaskedMemoryInit, ConfigPtr);
Status = LibSystemApiCall (AmdS3Init, ConfigPtr);
break;
case PH_AmdPcieS3Init :
Status = LibSystemApiCall (AmdS3InitIommu, ConfigPtr);
Status = LibSystemApiCall (AmdPcieS3Init, ConfigPtr);
break;
#endif
#ifdef B3_IMAGE
// B3 Functions
#endif
default:
break;
}
}
// 4. Try next dispatcher if possible, and we have not already got status back
if ((mNbModuleID.NextBlock != NULL) && (Status == AGESA_UNSUPPORTED)) {

56
src/vendorcode/amd/cimx/sb700/DISPATCHER.c
View File

@ -33,38 +33,17 @@
void DispatcherEntry(void *pConfig){
#ifdef B1_IMAGE
void *pB2ImagePtr = NULL;
CIM_IMAGE_ENTRY pB2ImageEntry;
#endif
//#if CIM_DEBUG
// InitSerialOut();
//#endif
TRACE((DMSG_SB_TRACE, "CIM - SB700 Entry\n"));
#ifdef B1_IMAGE
if ((UINT32)(((STDCFG*)pConfig)->pB2ImageBase) != 0xffffffff){
if (((STDCFG*)pConfig)->pB2ImageBase)
pB2ImagePtr = CheckImage('007S',(void*)((STDCFG*)pConfig)->pB2ImageBase);
if (pB2ImagePtr == NULL)
pB2ImagePtr = LocateImage('007S');
if (pB2ImagePtr!=NULL){
TRACE((DMSG_SB_TRACE, "CIM - SB700 Redirect to B2 Image\n"));
((STDCFG*)pConfig)->pImageBase = (UINT32)pB2ImagePtr;
pB2ImageEntry = (CIM_IMAGE_ENTRY)(*((UINT32*)pB2ImagePtr+1) + (UINT32)pB2ImagePtr);
(*pB2ImageEntry)(pConfig);
return;
}
}
#endif
saveConfigPointer(pConfig);
if (((STDCFG*)pConfig)->Func == SB_POWERON_INIT)
sbPowerOnInit((AMDSBCFG*)pConfig);
#ifndef B1_IMAGE
if (((STDCFG*)pConfig)->Func == SB_BEFORE_PCI_INIT)
sbBeforePciInit((AMDSBCFG*)pConfig);
if (((STDCFG*)pConfig)->Func == SB_AFTER_PCI_INIT)
@ -81,43 +60,10 @@ void DispatcherEntry(void *pConfig){
}
if (((STDCFG*)pConfig)->Func == SB_SMM_ACPION)
sbSmmAcpiOn((AMDSBCFG*)pConfig);
#endif
TRACE((DMSG_SB_TRACE, "CIMx - SB Exit\n"));
}
void* LocateImage(UINT32 Signature){
void *Result;
UINT8 *ImagePtr = (UINT8*)(0xffffffff - (IMAGE_ALIGN-1));
while ((UINTN)ImagePtr>=(0xfffffff - (NUM_IMAGE_LOCATION*IMAGE_ALIGN -1))){
Result = CheckImage(Signature,(void*)ImagePtr);
if (Result != NULL)
return Result;
ImagePtr -= IMAGE_ALIGN;
}
return NULL;
}
void* CheckImage(UINT32 Signature, void* ImagePtr){
UINT8 *TempImagePtr;
UINT8 Sum = 0;
UINT32 i;
// if ((*((UINT32*)ImagePtr) == 'ITA$' && ((CIMFILEHEADER*)ImagePtr)->ModuleLogo == Signature)){
if ((*((UINT32*)ImagePtr) == Int32FromChar ('$', 'A', 'T', 'I')) && (((CIMFILEHEADER*)ImagePtr)->ModuleLogo == Signature)){
//GetImage Image size
TempImagePtr = (UINT8*)ImagePtr;
for (i=0;i<(((CIMFILEHEADER*)ImagePtr)->ImageSize);i++){
Sum += *TempImagePtr;
TempImagePtr++;
}
if (Sum == 0)
return ImagePtr;
}
return NULL;
}
UINT32 GetPciebase(){
AMDSBCFG* Result;
Result = getConfigPointer();

2
src/vendorcode/amd/cimx/sb700/SBDEF.h
View File

@ -59,8 +59,6 @@ UINT32 IsFamily10(void);
UINT64 ReadMSR(UINT32 Address);
void WriteMSR(UINT32 Address,UINT64 Value);
void RWMSR(UINT32 Address, UINT64 Mask, UINT64 Value);
void* LocateImage(UINT32 Signature);
void* CheckImage( UINT32 Signature, void* ImagePtr);
void Stall(UINT32 uSec);
void Reset(void);
CIM_STATUS RWSMBUSBlock(UINT8 Controller, UINT8 Address, UINT8 Offset, UINT8 BufferSize, UINT8* BufferPrt);

4
src/vendorcode/amd/cimx/sb700/SBMAIN.c
View File

@ -31,8 +31,6 @@
#include "Platform.h"
#ifndef B1_IMAGE
BUILDPARAM DfltStaticOptions={
BIOS_SIZE, // BIOS Size
LEGACY_FREE, // Legacy Free Option
@ -285,5 +283,3 @@ UINT32 CallBackToOEM(UINT32 Func, UINTN Data,AMDSBCFG* pConfig){
TRACE((DMSG_SB_TRACE,"SB Hook Status [%x]\n",Result));
return Result;
}
#endif

87
src/vendorcode/amd/cimx/sb800/DISPATCHER.c
View File

@ -62,8 +62,6 @@
//
VOID saveConfigPointer (IN AMDSBCFG* pConfig);
VOID* VerifyImage (IN UINT64 Signature, IN VOID* ImagePtr);
VOID* LocateImage (IN UINT64 Signature);
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
@ -90,42 +88,17 @@ AmdSbDispatcher (
{
AGESA_STATUS Status;
#ifdef B1_IMAGE
VOID *pAltImagePtr;
CIM_IMAGE_ENTRY AltImageEntry;
#endif
UINT64 tdValue;
tdValue = 0x32314130384253ULL;
#ifdef B1_IMAGE
pAltImagePtr = NULL;
#endif
Status = AGESA_UNSUPPORTED;
#ifdef B1_IMAGE
if ((UINT32) (UINTN) (((AMD_CONFIG_PARAMS*)pConfig)->AltImageBasePtr) != 0xffffffff ) {
if ( ((AMD_CONFIG_PARAMS*)pConfig)->AltImageBasePtr ) {
pAltImagePtr = VerifyImage ( tdValue, (VOID*) (UINTN) ((AMD_CONFIG_PARAMS*)pConfig)->AltImageBasePtr);
}
if ( pAltImagePtr == NULL ) {
pAltImagePtr = LocateImage ( tdValue );
}
if ( pAltImagePtr != NULL ) {
((AMD_CONFIG_PARAMS*)pConfig)->ImageBasePtr = (UINT32) (UINTN) pAltImagePtr;
AltImageEntry = (CIM_IMAGE_ENTRY) (UINTN) ((UINT32) (UINTN) pAltImagePtr + (UINT32) (((AMD_IMAGE_HEADER*) (UINTN) pAltImagePtr)->EntryPointAddress));
(*AltImageEntry) (pConfig);
return Status;
}
}
#endif
saveConfigPointer (pConfig);
if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_POWERON_INIT ) {
sbPowerOnInit ((AMDSBCFG*) pConfig);
}
#ifndef B1_IMAGE
if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_BEFORE_PCI_INIT ) {
sbBeforePciInit ((AMDSBCFG*)pConfig);
}
@ -161,69 +134,9 @@ AmdSbDispatcher (
if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_EC_FANCONTROL ) {
sbECfancontrolservice((AMDSBCFG*)pConfig);
}
#endif
return Status;
}
/**
* LocateImage - Locate Southbridge CIMx module
*
*
*
* @param[in] Signature Southbridge CIMx image signature.
*
*/
VOID*
LocateImage (
IN UINT64 Signature
)
{
VOID *Result;
UINT32 ImagePtr;
ImagePtr = 0xffffffff - (IMAGE_ALIGN - 1);
while ( ImagePtr >= (0xfffffff - (NUM_IMAGE_LOCATION * IMAGE_ALIGN - 1)) ) {
Result = VerifyImage (Signature, (VOID*)(UINTN)ImagePtr);
if ( Result != NULL ) {
return Result;
}
ImagePtr -= IMAGE_ALIGN;
}
return NULL;
}
/**
* VerifyImage - Verify Southbridge CIMx module
*
*
* @param[in] Signature Southbridge CIMx image signature.
* @param[in] ImagePtr Southbridge CIMx image address.
*
*/
VOID*
VerifyImage (
IN UINT64 Signature,
IN VOID* ImagePtr
)
{
UINT16 *TempImagePtr;
UINT16 Sum;
UINT32 i;
Sum = 0;
if ( (*((UINT32*)ImagePtr) == Int32FromChar('$', 'A', 'M', 'D') && ((CIMFILEHEADER*)ImagePtr)->CreatorID == Signature) ) {
//GetImage Image size
TempImagePtr = (UINT16*)ImagePtr;
for ( i = 0; i < (((CIMFILEHEADER*)ImagePtr)->ImageSize); i += 2 ) {
Sum = Sum + *TempImagePtr;
TempImagePtr++;
}
if ( Sum == 0 ) {
return ImagePtr;
}
}
return NULL;
}
/**
* saveConfigPointer - Verify Southbridge CIMx module
*

4
src/vendorcode/amd/cimx/sb800/SBMAIN.c
View File

@ -46,8 +46,6 @@
#include "SBPLATFORM.h"
#include "cbtypes.h"
#ifndef B1_IMAGE
/*----------------------------------------------------------------------------------------*/
/**
* sbBeforePciInit - Config Southbridge before PCI emulation
@ -228,8 +226,6 @@ sbSmmAcpiOn (
RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGAC, AccWidthUint8, ~(BIT6 + BIT7), 0);
}
#endif
/*----------------------------------------------------------------------------------------*/
/**
* Call Back routine.

90
src/vendorcode/amd/cimx/sb900/Dispatcher.c
View File

@ -60,8 +60,6 @@
//
VOID saveConfigPointer (IN AMDSBCFG* pConfig);
VOID* VerifyImage (IN UINT64 Signature, IN VOID* ImagePtr);
VOID* LocateImage (IN UINT64 Signature);
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
@ -89,12 +87,6 @@ AmdSbDispatcher (
AGESA_STATUS Status;
UINT64 tdValue;
#ifdef B1_IMAGE
VOID *pAltImagePtr;
CIM_IMAGE_ENTRY AltImageEntry;
pAltImagePtr = NULL;
#endif
Status = AGESA_UNSUPPORTED;
tdValue = 0x313141324E4448ull;
@ -106,29 +98,12 @@ AmdSbDispatcher (
Status = AGESA_UNSUPPORTED;
TRACE ((DMSG_SB_TRACE, "CIM - Hudson-2 Entry\n"));
#ifdef B1_IMAGE
if ((UINT32) (UINTN) (((AMD_CONFIG_PARAMS*)pConfig)->AltImageBasePtr) != 0xffffffff ) {
if ( ((AMD_CONFIG_PARAMS*)pConfig)->AltImageBasePtr ) {
pAltImagePtr = VerifyImage ( tdValue, (VOID*) (UINTN) ((AMD_CONFIG_PARAMS*)pConfig)->AltImageBasePtr);
}
if ( pAltImagePtr == NULL ) {
pAltImagePtr = LocateImage ( tdValue );
}
if ( pAltImagePtr != NULL ) {
((AMD_CONFIG_PARAMS*)pConfig)->ImageBasePtr = (UINT32) (UINTN) pAltImagePtr;
AltImageEntry = (CIM_IMAGE_ENTRY) (UINTN) ((UINT32) (UINTN) pAltImagePtr + (UINT32) (((AMD_IMAGE_HEADER*) (UINTN) pAltImagePtr)->EntryPointAddress));
(*AltImageEntry) (pConfig);
return Status;
}
}
#endif
saveConfigPointer (pConfig);
if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_POWERON_INIT ) {
sbPowerOnInit ((AMDSBCFG*) pConfig);
}
#ifndef B1_IMAGE
if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_BEFORE_PCI_INIT ) {
sbBeforePciInit ((AMDSBCFG*)pConfig);
}
@ -164,75 +139,10 @@ AmdSbDispatcher (
if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_EC_FANCONTROL ) {
sbECfancontrolservice ((AMDSBCFG*)pConfig);
}
#endif
TRACE ((DMSG_SB_TRACE, "CIMx - SB Exit\n"));
return Status;
}
/**
* LocateImage - Locate Southbridge CIMx module
*
*
*
* @param[in] Signature Southbridge CIMx image signature.
*
*/
VOID*
LocateImage (
IN UINT64 Signature
)
{
VOID *Result;
UINT32 ImagePtr;
ImagePtr = 0xffffffff - (IMAGE_ALIGN - 1);
while ( ImagePtr >= (0xfffffff - (NUM_IMAGE_LOCATION * IMAGE_ALIGN - 1)) ) {
#ifdef x64
12346789
#else
Result = VerifyImage (Signature, (VOID*) (intptr_t) ImagePtr);
#endif
if ( Result != NULL ) {
return Result;
}
ImagePtr -= IMAGE_ALIGN;
}
return NULL;
}
/**
* VerifyImage - Verify Southbridge CIMx module
*
*
* @param[in] Signature Southbridge CIMx image signature.
* @param[in] ImagePtr Southbridge CIMx image address.
*
*/
VOID*
VerifyImage (
IN UINT64 Signature,
IN VOID* ImagePtr
)
{
UINT16 *TempImagePtr;
UINT16 Sum;
UINT32 i;
Sum = 0;
// if ( (*((UINT32*)ImagePtr) == 'DMA$' && ((CIMFILEHEADER*)ImagePtr)->CreatorID == Signature) ) {
if ( (*((UINT32*)ImagePtr) == Int32FromChar('D', 'M', 'A', '$') && ((CIMFILEHEADER*)ImagePtr)->CreatorID == Signature) ) {
//GetImage Image size
TempImagePtr = (UINT16*)ImagePtr;
for ( i = 0; i < (((CIMFILEHEADER*)ImagePtr)->ImageSize); i += 2 ) {
Sum = Sum + *TempImagePtr;
TempImagePtr++;
}
if ( Sum == 0 ) {
return ImagePtr;
}
}
return NULL;
}
/**
* saveConfigPointer - Verify Southbridge CIMx module
*

4
src/vendorcode/amd/cimx/sb900/SbMain.c
View File

@ -44,8 +44,6 @@
#include "cbtypes.h"
#include "AmdSbLib.h"
#ifndef B1_IMAGE
/*----------------------------------------------------------------------------------------*/
/**
* sbBeforePciInit - Config Southbridge before PCI emulation
@ -263,8 +261,6 @@ sbSmmAcpiOn (
//RWMEM (0x20, AccWidthUint32, 0, 0);
}
#endif
/*----------------------------------------------------------------------------------------*/
/**
* Call Back routine.