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soc/mediatek/mt8183: Fix wrong setting of DRS config 

Update setting of DRS config.

BUG=none
BRANCH=kukui
TEST=Boots correctly on Kukui

Change-Id: Id38fc224b54c3947af8bbc5c1a4a8d70eb53d5fb
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This commit is contained in:
Huayang Duan 2020-03-18 13:49:00 +08:00 committed by Patrick Georgi
parent c4917775fd
commit 31b081a48d
1 changed files with 4 additions and 3 deletions
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7
src/soc/mediatek/mt8183/dramc_pi_basic_api.c
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@ -485,9 +485,10 @@ void dramc_runtime_config(void)
/* DRAM DRS DISABLE */ /* DRAM DRS DISABLE */
clrsetbits32(&ch[chn].ao.drsctrl, clrsetbits32(&ch[chn].ao.drsctrl,
(0x1 << 21) | (0x3f << 12) | (0xf << 8) | (0x1 << 6), (0x1 << 0) | (0x1 << 2) | (0x1 << 4) | (0x1 << 5) | (0x1 << 6) |
(0x1 << 19) | (0x3 << 12) | (0x8 << 8) | (0xf << 8) | (0x7f << 12) | (0x1 << 19) | (0x1 << 21),
(0x3 << 4) | (0x1 << 2) | (0x1 << 0)); (0x1 << 0) | (0x0 << 2) | (0x0 << 4) | (0x1 << 5) | (0x0 << 6) |
(0x8 << 8) | (0x3 << 12) | (0x1 << 19) | (0x0 << 21));
setbits32(&ch[chn].ao.dummy_rd, 0x3 << 26); setbits32(&ch[chn].ao.dummy_rd, 0x3 << 26);
} }
dramc_dqs_precalculation_preset(); dramc_dqs_precalculation_preset();