Instead of requiring users to modify qemu to allow writes to
0xc0000-0xfffff, have coreboot qemu support enable the memory range at startup. Signed-off-by: Kevin O'Connor <kevin@koconnor.net> Acked-by: Myles Watson <mylesgw@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -10,15 +10,15 @@
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/* not sure how these are routed in qemu */
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static const unsigned char enetIrqs[4] = { 11, 0, 0, 0 };
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static void qemu_init(device_t dev)
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static void qemu_nb_init(device_t dev)
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{
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/* The VGA OPROM already lives at 0xc0000,
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* force coreboot to use it.
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*/
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dev->on_mainboard = 1;
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/* Now do the usual initialization */
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pci_dev_init(dev);
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/* Map memory at 0xc0000 - 0xfffff */
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int i;
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uint8_t v = pci_read_config8(dev, 0x59);
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v |= 0x30;
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pci_write_config8(dev, 0x59, v);
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for (i=0; i<6; i++)
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pci_write_config8(dev, 0x5a + i, 0x33);
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/* This sneaked in here, because Qemu does not
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* emulate a SuperIO chip
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@ -32,6 +32,31 @@ static void qemu_init(device_t dev)
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pci_assign_irqs(0, 3, enetIrqs);
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}
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static struct device_operations nb_operations = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = qemu_nb_init,
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.ops_pci = 0,
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};
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static const struct pci_driver nb_driver __pci_driver = {
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.ops = &nb_operations,
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.vendor = 0x8086,
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.device = 0x1237,
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};
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static void qemu_init(device_t dev)
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{
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/* The VGA OPROM already lives at 0xc0000,
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* force coreboot to use it.
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*/
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dev->on_mainboard = 1;
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/* Now do the usual initialization */
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pci_dev_init(dev);
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}
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static struct device_operations vga_operations = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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