AMD Inagua: Use SPD read code from F14 wrapper
Changes: - Get rid of the inagua mainboard specific code and use the platform generic function wrapper that was added in change http://review.coreboot.org/#/c/2497/ AMD f14: Add SPD read functions to wrapper code - Move DIMM addresses into devicetree.cb - Add the ASF init that used to be in the SPD read code into mainboard_enable() Notes: - The DIMM reads only happen in romstage, so the function is not available in ramstage. Point the read-SPD callback to a generic function in ramstage. Change-Id: Id05227fcf18c6ab94ffe1beb50b533ab7b0535db Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com> Reviewed-on: http://review.coreboot.org/2607 Reviewed-by: Martin Roth <martin.roth@se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Kimarie Hoot
Martin Roth
parent
a5ddac02f4
commit
31c5e07a04
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@ -19,10 +19,10 @@
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#include "agesawrapper.h"
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#include "amdlib.h"
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#include "dimmSpd.h"
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#include "BiosCallOuts.h"
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#include "heapManager.h"
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#include "SB800.h"
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#include <northbridge/amd/agesa/family14/dimmSpd.h>
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STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] =
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{
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@ -419,7 +419,11 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
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AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
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{
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AGESA_STATUS Status;
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Status = AmdMemoryReadSPD (Func, Data, (AGESA_READ_SPD_PARAMS *)ConfigPtr);
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#ifdef __PRE_RAM__
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Status = agesa_ReadSPD (Func, Data, ConfigPtr);
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#else
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Status = AGESA_UNSUPPORTED;
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#endif
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return Status;
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}
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@ -26,13 +26,11 @@ endif
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romstage-y += buildOpts.c
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romstage-y += agesawrapper.c
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romstage-y += dimmSpd.c
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romstage-y += BiosCallOuts.c
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romstage-y += PlatformGnbPcie.c
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ramstage-y += buildOpts.c
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ramstage-y += agesawrapper.c
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ramstage-y += dimmSpd.c
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ramstage-y += BiosCallOuts.c
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ramstage-y += PlatformGnbPcie.c
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@ -86,6 +86,11 @@ chip northbridge/amd/agesa/family14/root_complex
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device pci 18.5 on end
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device pci 18.6 on end
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device pci 18.7 on end
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register "spdAddrLookup" = "
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{
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{ {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
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}"
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end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
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end #domain
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end #northbridge/amd/agesa/family14/root_complex
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@ -1,159 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "Porting.h"
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#include "AGESA.h"
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#include "amdlib.h"
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#include "OEM.h" /* SMBUS0_BASE_ADDRESS */
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AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info);
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#define DIMENSION(array)(sizeof (array)/ sizeof (array [0]))
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/*#pragma optimize ("", off) // for source level debug
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*---------------------------------------------------------------------------
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*
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* SPD address table - porting required
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*/
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static const UINT8 spdAddressLookup [1] [2] [2] = // socket, channel, dimm
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{
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// socket 0
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{
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{0xA0, 0xA2}, // channel 0 dimms
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{0x00, 0x00}, // channel 1 dimms
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},
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};
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/*-----------------------------------------------------------------------------
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*
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* readSmbusByteData - read a single SPD byte from any offset
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*/
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static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
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{
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unsigned int status;
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UINT64 limit;
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address |= 1; // set read bit
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__outbyte (iobase + 0, 0xFF); // clear error status
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__outbyte (iobase + 1, 0x1F); // clear error status
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__outbyte (iobase + 3, offset); // offset in eeprom
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__outbyte (iobase + 4, address); // slave address and read bit
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__outbyte (iobase + 2, 0x48); // read byte command
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// time limit to avoid hanging for unexpected error status (should never happen)
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limit = __rdtsc () + 2000000000 / 10;
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for (;;) {
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status = __inbyte (iobase);
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if (__rdtsc () > limit) break;
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if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting
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if ((status & 1) == 1) continue; // HostBusy set, keep waiting
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break;
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}
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buffer [0] = __inbyte (iobase + 5);
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if (status == 2) status = 0; // check for done with no errors
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return status;
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}
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/*-----------------------------------------------------------------------------
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*
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* readSmbusByte - read a single SPD byte from the default offset
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* this function is faster function readSmbusByteData
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*/
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static int readSmbusByte (int iobase, int address, char *buffer)
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{
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unsigned int status;
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UINT64 limit;
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__outbyte (iobase + 0, 0xFF); // clear error status
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__outbyte (iobase + 2, 0x44); // read command
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// time limit to avoid hanging for unexpected error status
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limit = __rdtsc () + 2000000000 / 10;
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for (;;) {
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status = __inbyte (iobase);
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if (__rdtsc () > limit) break;
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if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting
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if ((status & 1) == 1) continue; // HostBusy set, keep waiting
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break;
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}
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buffer [0] = __inbyte (iobase + 5);
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if (status == 2) status = 0; // check for done with no errors
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return status;
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}
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/*---------------------------------------------------------------------------
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*
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* readspd - Read one or more SPD bytes from a DIMM.
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* Start with offset zero and read sequentially.
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* Optimization relies on autoincrement to avoid
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* sending offset for every byte.
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* Reads 128 bytes in 7-8 ms at 400 KHz.
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*/
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static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count)
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{
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int index, error;
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/* read the first byte using offset zero */
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error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0);
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if (error) return error;
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/* read the remaining bytes using auto-increment for speed */
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for (index = 1; index < count; index++) {
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error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]);
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if (error) return error;
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}
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return 0;
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}
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static void writePmReg (int reg, int data)
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{
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__outbyte (0xCD6, reg);
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__outbyte (0xCD7, data);
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}
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static void setupFch (int ioBase)
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{
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writePmReg (0x2D, ioBase >> 8);
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writePmReg (0x2C, ioBase | 1);
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writePmReg (0x29, 0x80);
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writePmReg (0x28, 0x61);
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__outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz
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}
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AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info)
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{
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int spdAddress, ioBase;
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if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR;
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if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR;
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if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR;
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spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId];
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if (spdAddress == 0) return AGESA_ERROR;
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ioBase = SMBUS0_BASE_ADDRESS;
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setupFch (ioBase);
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return readspd (ioBase, spdAddress, (void *) info->Buffer, 128);
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}
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@ -1,63 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*----------------------------------------------------------------------------------------
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* M O D U L E S U S E D
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*----------------------------------------------------------------------------------------
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*/
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#ifndef _DIMMSPD_H_
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#define _DIMMSPD_H_
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#include "Porting.h"
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#include "AGESA.h"
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/*----------------------------------------------------------------------------------------
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* D E F I N I T I O N S A N D M A C R O S
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*----------------------------------------------------------------------------------------
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*/
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/*----------------------------------------------------------------------------------------
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* T Y P E D E F S A N D S T R U C T U R E S
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*----------------------------------------------------------------------------------------
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*/
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/*----------------------------------------------------------------------------------------
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* P R O T O T Y P E S O F L O C A L F U N C T I O N S
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*----------------------------------------------------------------------------------------
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*/
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/*----------------------------------------------------------------------------------------
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* E X P O R T E D F U N C T I O N S
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*----------------------------------------------------------------------------------------
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*/
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AGESA_STATUS
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AmdMemoryReadSPD (
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IN UINT32 Func,
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IN UINT32 Data,
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IN OUT AGESA_READ_SPD_PARAMS *SpdData
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);
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/*---------------------------------------------------------------------------------------
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* L O C A L F U N C T I O N S
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*---------------------------------------------------------------------------------------
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*/
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#endif
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@ -24,7 +24,7 @@
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#include <cpu/x86/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <device/pci_def.h>
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//#include <southbridge/amd/sb800/sb800.h>
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#include <southbridge/amd/sb800/sb800.h>
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#include "SBPLATFORM.h" /* Platfrom Specific Definitions */
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void set_pcie_reset(void);
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@ -79,6 +79,15 @@ static void mainboard_enable(device_t dev)
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/* Inagua mainboard specific setting */
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set_pcie_dereset();
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/*
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* Initialize ASF registers to an arbitrary address because someone
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* long ago set things up this way inside the SPD read code. The
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* SPD read code has been made generic and moved out of the board
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* directory, so the ASF init is being done here.
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*/
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pm_iowrite(0x29, 0x80);
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pm_iowrite(0x28, 0x61);
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}
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struct chip_operations mainboard_ops = {
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