PCIe: Add L1 Sub-State support.
Enable L1 Sub-State when both root port and endpoint support it. [pg: keyed the feature to MMCONF_SUPPORT, otherwise boards without that capability fail to build.] Change-Id: Id11fc7c73eb865411747eef63f5f901e00a17f84 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6ac04ad7e2261846e40da297f7fa317ccebda092 Original-BUG=chrome-os-partner:31424 Original-TEST=Build a image and run on Samus proto boards to check if the settings are applied correctly. I just only have proto boards and need someone having EVT boards to confirm the settings. Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Original-Change-Id: Id1b5a52ff0b896f4531c4a6e68e70a2cea8c736a Original-Reviewed-on: https://chromium-review.googlesource.com/221436 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/8832 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Kenji Chen
Patrick Georgi
parent
431e51ec2a
commit
31c6e632cf
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@ -271,6 +271,14 @@ config EARLY_PCI_BRIDGE
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This option enables static configuration for a single pre-defined
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PCI bridge function on bus 0.
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config PCIEXP_L1_SUB_STATE
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prompt "Enable PCIe ASPM L1 SubState"
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bool
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depends on PCIEXP_PLUGIN_SUPPORT && MMCONF_SUPPORT
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default n
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help
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Detect and enable ASPM on PCIe links.
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if EARLY_PCI_BRIDGE
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config EARLY_PCI_BRIDGE_DEVICE
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@ -25,6 +25,31 @@
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#include <device/pci_ids.h>
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#include <device/pciexp.h>
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#if IS_ENABLED(CONFIG_MMCONF_SUPPORT)
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unsigned int pciexp_find_extended_cap(device_t dev, unsigned int cap)
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{
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unsigned int this_cap_offset, next_cap_offset;
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unsigned int this_cap, cafe;
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this_cap_offset = PCIE_EXT_CAP_OFFSET;
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do {
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this_cap = pci_mmio_read_config32(dev, this_cap_offset);
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next_cap_offset = this_cap >> 20;
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this_cap &= 0xffff;
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cafe = pci_mmio_read_config32(dev, this_cap_offset + 4);
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cafe &= 0xffff;
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if (this_cap == cap)
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return this_cap_offset;
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else if (cafe == cap)
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return this_cap_offset + 4;
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else
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this_cap_offset = next_cap_offset;
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} while (next_cap_offset != 0);
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return 0;
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}
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#endif
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#if CONFIG_PCIEXP_COMMON_CLOCK
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/*
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* Re-train a PCIe link
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@ -107,6 +132,160 @@ static void pciexp_enable_clock_power_pm(device_t endp, unsigned endp_cap)
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}
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#endif /* CONFIG_PCIEXP_CLK_PM */
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#if IS_ENABLED(CONFIG_PCIEXP_L1_SUB_STATE) && IS_ENABLED(CONFIG_MMCONF_SUPPORT)
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static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or)
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{
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u32 reg32;
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reg32 = pci_mmio_read_config32(dev, reg);
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reg32 &= mask;
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reg32 |= or;
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pci_mmio_write_config32(dev, reg, reg32);
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}
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static void pciexp_config_max_latency(device_t root, device_t dev)
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{
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unsigned int cap;
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cap = pciexp_find_extended_cap(dev, PCIE_EXT_CAP_LTR_ID);
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if (root->ops->ops_pci->set_L1_ss_latency != NULL)
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root->ops->ops_pci->set_L1_ss_latency(dev, cap + 4);
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}
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static void pciexp_enable_ltr(device_t dev)
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{
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unsigned int cap;
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cap = pci_find_capability(dev, PCI_CAP_ID_PCIE);
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pcie_update_cfg(dev, cap + 0x28, ~(1 << 10), 1 << 10);
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}
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static unsigned char pciexp_L1_substate_cal(device_t dev, unsigned int endp_cap,
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unsigned int *data)
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{
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unsigned char mult[4] = {2, 10, 100, 0};
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unsigned int L1SubStateSupport = *data & 0xf;
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unsigned int comm_mode_rst_time = (*data >> 8) & 0xff;
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unsigned int power_on_scale = (*data >> 16) & 0x3;
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unsigned int power_on_value = (*data >> 19) & 0x1f;
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unsigned int endp_data = pci_mmio_read_config32(dev, endp_cap + 4);
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unsigned int endp_L1SubStateSupport = endp_data & 0xf;
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unsigned int endp_comm_mode_restore_time = (endp_data >> 8) & 0xff;
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unsigned int endp_power_on_scale = (endp_data >> 16) & 0x3;
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unsigned int endp_power_on_value = (endp_data >> 19) & 0x1f;
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L1SubStateSupport &= endp_L1SubStateSupport;
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if (L1SubStateSupport == 0)
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return 0;
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if (power_on_value * mult[power_on_scale] <
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endp_power_on_value * mult[endp_power_on_scale]) {
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power_on_value = endp_power_on_value;
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power_on_scale = endp_power_on_scale;
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}
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if (comm_mode_rst_time < endp_comm_mode_restore_time)
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comm_mode_rst_time = endp_comm_mode_restore_time;
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*data = (comm_mode_rst_time << 8) | (power_on_scale << 16)
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| (power_on_value << 19) | L1SubStateSupport;
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return 1;
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}
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static void pciexp_L1_substate_commit(device_t root, device_t dev,
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unsigned int root_cap, unsigned int end_cap)
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{
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device_t dev_t;
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unsigned char L1_ss_ok;
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unsigned int rp_L1_support = pci_mmio_read_config32(root, root_cap + 4);
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unsigned int L1SubStateSupport;
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unsigned int comm_mode_rst_time;
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unsigned int power_on_scale;
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unsigned int endp_power_on_value;
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for (dev_t = dev; dev_t; dev_t = dev_t->sibling) {
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/*
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* rp_L1_support is init'd above from root port.
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* it needs coordination with endpoints to reach in common.
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* if certain endpoint doesn't support L1 Sub-State, abort
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* this feature enabling.
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*/
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L1_ss_ok = pciexp_L1_substate_cal(dev_t, end_cap,
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&rp_L1_support);
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if (!L1_ss_ok)
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return;
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}
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L1SubStateSupport = rp_L1_support & 0xf;
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comm_mode_rst_time = (rp_L1_support >> 8) & 0xff;
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power_on_scale = (rp_L1_support >> 16) & 0x3;
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endp_power_on_value = (rp_L1_support >> 19) & 0x1f;
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printk(BIOS_INFO, "L1 Sub-State supported from root port %d\n",
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root->path.pci.devfn >> 3);
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printk(BIOS_INFO, "L1 Sub-State Support = 0x%x\n", L1SubStateSupport);
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printk(BIOS_INFO, "CommonModeRestoreTime = 0x%x\n", comm_mode_rst_time);
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printk(BIOS_INFO, "Power On Value = 0x%x, Power On Scale = 0x%x\n",
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endp_power_on_value, power_on_scale);
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pciexp_enable_ltr(root);
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pcie_update_cfg(root, root_cap + 0x08, ~0xff00,
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(comm_mode_rst_time << 8));
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pcie_update_cfg(root, root_cap + 0x0c , 0xffffff04,
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(endp_power_on_value << 3) | (power_on_scale));
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pcie_update_cfg(root, root_cap + 0x08, ~0xe3ff0000,
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(1 << 21) | (1 << 23) | (1 << 30));
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pcie_update_cfg(root, root_cap + 0x08, ~0xf,
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L1SubStateSupport);
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for (dev_t = dev; dev_t; dev_t = dev_t->sibling) {
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pcie_update_cfg(dev_t, end_cap + 0x08, ~0xff00,
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(comm_mode_rst_time << 8));
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pcie_update_cfg(dev_t, end_cap + 0x0c , 0xffffff04,
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(endp_power_on_value << 3) | (power_on_scale));
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pcie_update_cfg(dev_t, end_cap + 0x08, ~0xe3ff0000,
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(1 << 21) | (1 << 23) | (1 << 30));
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pcie_update_cfg(dev_t, end_cap + 0x08, ~0xf,
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L1SubStateSupport);
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pciexp_enable_ltr(dev_t);
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pciexp_config_max_latency(root, dev_t);
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}
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}
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static void pciexp_config_L1_sub_state(device_t root, device_t dev)
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{
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unsigned int root_cap, end_cap;
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/* Do it for function 0 only */
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if (dev->path.pci.devfn & 0x7)
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return;
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root_cap = pciexp_find_extended_cap(root, PCIE_EXT_CAP_L1SS_ID);
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if (!root_cap)
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return;
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end_cap = pciexp_find_extended_cap(dev, PCIE_EXT_CAP_L1SS_ID);
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if (!end_cap) {
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end_cap = pciexp_find_extended_cap(dev, 0xcafe);
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if (!end_cap)
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return;
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}
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pciexp_L1_substate_commit(root, dev, root_cap, end_cap);
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}
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#endif /* CONFIG_PCIEXP_L1_SUB_STATE */
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#if CONFIG_PCIEXP_ASPM
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/*
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* Determine the ASPM L0s or L1 exit latency for a link
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@ -222,6 +401,11 @@ static void pciexp_tune_dev(device_t dev)
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pciexp_enable_clock_power_pm(dev, cap);
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#endif
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#if CONFIG_PCIEXP_L1_SUB_STATE
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/* Enable L1 Sub-State when both root port and endpoint support */
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pciexp_config_L1_sub_state(root, dev);
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#endif /* CONFIG_PCIEXP_L1_SUB_STATE */
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#if CONFIG_PCIEXP_ASPM
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/* Check for and enable ASPM */
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enum aspm_type apmc = pciexp_enable_aspm(root, root_cap, dev, cap);
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@ -33,6 +33,7 @@
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struct pci_operations {
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/* set the Subsystem IDs for the PCI device */
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void (*set_subsystem)(device_t dev, unsigned vendor, unsigned device);
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void (*set_L1_ss_latency)(device_t dev, unsigned int off);
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};
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/* Common pci bus operations */
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@ -405,6 +405,12 @@
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#define PCI_EXT_CAP_ID_DSN 3
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#define PCI_EXT_CAP_ID_PWR 4
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/* Extended Capability lists*/
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#define PCIE_EXT_CAP_OFFSET 0x100
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#define PCIE_EXT_CAP_AER_ID 0x0001
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#define PCIE_EXT_CAP_L1SS_ID 0x001E
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#define PCIE_EXT_CAP_LTR_ID 0x0018
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/* Advanced Error Reporting */
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#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */
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#define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */
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@ -15,4 +15,5 @@ unsigned int pciexp_scan_bridge(device_t dev, unsigned int max);
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extern struct device_operations default_pciexp_ops_bus;
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unsigned int pciexp_find_extended_cap(device_t dev, unsigned int cap);
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#endif /* DEVICE_PCIEXP_H */
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