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soc/amd/common/block/gpio_banks: Use configure_scimap() 

There is no need to stash the SCI trigger register configuration and
apply it at the end. Remove this to make SCI and SMI programming more
symmetrical and to use available configure_scimap function instead of
implementing it again, but without the additional checks. Using this
function also allows removing soc_route_sci.

Change-Id: Ie23da79546858282910db65182a6315ade506279
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Kyösti Mälkki 2020-07-02 20:46:25 +03:00 committed by Felix Held
parent 70c7013102
commit 31d49ec117
3 changed files with 12 additions and 46 deletions
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52
src/soc/amd/common/block/gpio_banks/gpio.c
View File

@ -45,12 +45,6 @@ static void program_smi(uint32_t flags, int gevent_num)
configure_gevent_smi(gevent_num, SMI_MODE_SMI, level); configure_gevent_smi(gevent_num, SMI_MODE_SMI, level);
} }
struct sci_trigger_regs {
uint32_t mask;
uint32_t polarity;
uint32_t level;
};
/* /*
* For each general purpose event, GPE, the choice of edge/level triggered * For each general purpose event, GPE, the choice of edge/level triggered
* event is represented as a single bit in SMI_SCI_LEVEL register. * event is represented as a single bit in SMI_SCI_LEVEL register.
@ -58,37 +52,24 @@ struct sci_trigger_regs {
* In a similar fashion, polarity (rising/falling, hi/lo) of each GPE is * In a similar fashion, polarity (rising/falling, hi/lo) of each GPE is
* represented as a single bit in SMI_SCI_TRIG register. * represented as a single bit in SMI_SCI_TRIG register.
*/ */
static void fill_sci_trigger(uint32_t flags, int gpe, struct sci_trigger_regs *regs) static void program_sci(uint32_t flags, int gevent_num)
{ {
uint32_t mask = 1 << gpe; struct sci_source sci;
regs->mask |= mask; sci.scimap = gevent_num;
sci.gpe = gevent_num;
if (is_gpio_event_level_triggered(flags)) if (is_gpio_event_level_triggered(flags))
regs->level |= mask; sci.level = SMI_SCI_LVL;
else else
regs->level &= ~mask; sci.level = SMI_SCI_EDG;
if (is_gpio_event_active_high(flags)) if (is_gpio_event_active_high(flags))
regs->polarity |= mask; sci.direction = SMI_SCI_LVL_HIGH;
else else
regs->polarity &= ~mask; sci.direction = SMI_SCI_LVL_LOW;
}
/* TODO: See configure_scimap() implementations. */ configure_scimap(&sci);
static void set_sci_trigger(const struct sci_trigger_regs *regs)
{
uint32_t value;
value = smi_read32(SMI_SCI_TRIG);
value &= ~regs->mask;
value |= regs->polarity;
smi_write32(SMI_SCI_TRIG, value);
value = smi_read32(SMI_SCI_LEVEL);
value &= ~regs->mask;
value |= regs->level;
smi_write32(SMI_SCI_LEVEL, value);
} }
uintptr_t gpio_get_address(gpio_t gpio_num) uintptr_t gpio_get_address(gpio_t gpio_num)
@ -179,8 +160,7 @@ uint16_t gpio_acpi_pin(gpio_t gpio)
return gpio; return gpio;
} }
static void set_single_gpio(const struct soc_amd_gpio *g, static void set_single_gpio(const struct soc_amd_gpio *g)
struct sci_trigger_regs *sci_trigger_cfg)
{ {
static const struct soc_amd_event *gev_tbl; static const struct soc_amd_event *gev_tbl;
static size_t gev_items; static size_t gev_items;
@ -214,16 +194,12 @@ static void set_single_gpio(const struct soc_amd_gpio *g,
if (g->flags & GPIO_FLAG_SMI) { if (g->flags & GPIO_FLAG_SMI) {
program_smi(g->flags, gevent_num); program_smi(g->flags, gevent_num);
} else if (g->flags & GPIO_FLAG_SCI) { } else if (g->flags & GPIO_FLAG_SCI) {
fill_sci_trigger(g->flags, gevent_num, sci_trigger_cfg); program_sci(g->flags, gevent_num);
soc_route_sci(gevent_num);
} }
} }
void program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size) void program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size)
{ {
struct sci_trigger_regs sci_trigger_cfg = { 0 };
const bool can_set_smi_flags = !(CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) &&
ENV_SEPARATE_VERSTAGE);
size_t i; size_t i;
if (!gpio_list_ptr || !size) if (!gpio_list_ptr || !size)
@ -242,7 +218,7 @@ void program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size)
master_switch_clr(GPIO_MASK_STS_EN | GPIO_INTERRUPT_EN); master_switch_clr(GPIO_MASK_STS_EN | GPIO_INTERRUPT_EN);
for (i = 0; i < size; i++) for (i = 0; i < size; i++)
set_single_gpio(&gpio_list_ptr[i], &sci_trigger_cfg); set_single_gpio(&gpio_list_ptr[i]);
/* /*
* Re-enable interrupt status generation. * Re-enable interrupt status generation.
@ -252,10 +228,6 @@ void program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size)
* to be missed during boot. * to be missed during boot.
*/ */
master_switch_set(GPIO_INTERRUPT_EN); master_switch_set(GPIO_INTERRUPT_EN);
/* Set all SCI trigger polarity (high/low) and level (edge/level). */
if (can_set_smi_flags)
set_sci_trigger(&sci_trigger_cfg);
} }
int gpio_interrupt_status(gpio_t gpio) int gpio_interrupt_status(gpio_t gpio)

1
src/soc/amd/common/block/include/amdblocks/smi.h
View File

@ -46,7 +46,6 @@ void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level);
void configure_scimap(const struct sci_source *sci); void configure_scimap(const struct sci_source *sci);
void disable_gevent_smi(uint8_t gevent); void disable_gevent_smi(uint8_t gevent);
void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes); void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes);
void soc_route_sci(uint8_t event);
void clear_all_smi_status(void); void clear_all_smi_status(void);
void clear_smi_sci_status(void); void clear_smi_sci_status(void);

5
src/soc/amd/common/block/smi/smi_util.c
View File

@ -72,11 +72,6 @@ void southbridge_smi_set_eos(void)
smi_write32(SMI_REG_SMITRIG0, reg); smi_write32(SMI_REG_SMITRIG0, reg);
} }
void soc_route_sci(uint8_t event)
{
smi_write8(SMI_SCI_MAP(event), event);
}
/** /**
* Configure generation of SCIs. * Configure generation of SCIs.
*/ */