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soc/intel/meteorlake: Increase pcie snoop/non-snoop latency 

This fixes an issue where pcie was not power gating and blocked
S0ix entry. Overwrite pcie max non-snoop and snoop latency tolerance
values to 15.73ms as stated in doc #729123 - MTL External Design
Specification.

BUG=none
TEST=Boot google/rex, print/check values.

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.corp-partner.google.com>
Change-Id: I9dfb9edbac95d28d50653777466ea172be64f612
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68308
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Ravi Sarawadi 2022-10-12 00:05:41 -07:00 committed by Sridhar Siricilla
parent d4a7dceaa5
commit 31e0aeb747
1 changed files with 12 additions and 0 deletions
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12
src/soc/intel/meteorlake/Kconfig
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@ -385,4 +385,16 @@ config DROP_CPU_FEATURE_PROGRAM_IN_FSP
This feature is default enabled, in case of "coreboot running MP init"
aka MP_SERVICES_PPI_V2_NOOP config is selected.
config PCIE_LTR_MAX_SNOOP_LATENCY
hex
default 0x100f
help
Latency tolerance reporting, max snoop latency value defaults to 15.73 ms.
config PCIE_LTR_MAX_NO_SNOOP_LATENCY
hex
default 0x100f
help
Latency tolerance reporting, max non-snoop latency value defaults to 15.73 ms.
endif