soc/mediatek/mt8183: Improve code formatting
This patch contains some minor changes including: - Use lowercase hex literals - Combine short lines - Remove unnecessary curly braces - Simplify struct initialization - Leverage macro _SELPH_DQS_BITS - Ensure whitespaces around binary operators - Remove extra whitespaces after commas - Change log level and remove unnecessary debug logs BUG=none BRANCH=kukui TEST=emerge-kukui coreboot Change-Id: I33616e6142325920c2fd7e6dc1dc88eb29c5cf34 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This commit is contained in:
Yu-Ping Wu
Patrick Georgi
parent
ffb5ea3dc4
commit
31ec0c4fdc
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@ -67,13 +67,13 @@ static void ddr_phy_pll_setting(u8 chn, u8 freq_group)
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mid_cap_sel = 0x2;
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cap_sel = 0x0;
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sdm_pcw = 0x7b00;
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delta = 0xC03;
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delta = 0xc03;
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break;
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case LP4X_DDR3600:
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mid_cap_sel = 0x1;
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cap_sel = 0x0;
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sdm_pcw = 0x8a00;
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delta = 0xD96;
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delta = 0xd96;
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break;
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default:
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die("Invalid DDR frequency group %u\n", freq_group);
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@ -86,16 +86,16 @@ static void ddr_phy_pll_setting(u8 chn, u8 freq_group)
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ca_dll_mode[CHANNEL_A] = DLL_MASTER;
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ca_dll_mode[CHANNEL_B] = DLL_SLAVE;
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clrbits_le32(&ch[chn].phy.shu[0].pll[4], 0xFFFF);
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clrbits_le32(&ch[chn].phy.shu[0].pll[6], 0xFFFF);
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clrbits_le32(&ch[chn].phy.shu[0].pll[4], 0xffff);
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clrbits_le32(&ch[chn].phy.shu[0].pll[6], 0xffff);
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setbits_le32(&ch[chn].phy.misc_shu_opt, (chn + 1) << 18);
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clrsetbits_le32(&ch[chn].phy.ckmux_sel, 0x3 << 18 | 0x3 << 16, 0x0);
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clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[0], 0x3 << 18, 0x1 << 18);
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if (ca_dll_mode[chn] == DLL_SLAVE)
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clrsetbits_le32(&ch[chn].ao.dvfsdll, 0x1 << 1, 0x1 << 1);
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setbits_le32(&ch[chn].ao.dvfsdll, 0x1 << 1);
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else
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clrsetbits_le32(&ch[chn].ao.dvfsdll, 0x1 << 1, 0x0 << 1);
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clrbits_le32(&ch[chn].ao.dvfsdll, 0x1 << 1);
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bool is_master = (ca_dll_mode[chn] == DLL_MASTER);
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u8 phdet_out = is_master ? 0x0 : 0x1;
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@ -120,8 +120,7 @@ static void ddr_phy_pll_setting(u8 chn, u8 freq_group)
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(pd_ck_sel << 2) | (fastpj_ck_sel << 0));
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clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[6],
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0x1 << 7,
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(is_master ? 0x1 : 0x0) << 7);
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0x1 << 7, (is_master ? 0x1 : 0x0) << 7);
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struct reg_value regs_bak[] = {
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{&ch[chn].phy.b[0].dq[7]},
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@ -132,10 +131,9 @@ static void ddr_phy_pll_setting(u8 chn, u8 freq_group)
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for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++)
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regs_bak[i].value = read32(regs_bak[i].addr);
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for (size_t b = 0; b < 2; b++) {
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for (size_t b = 0; b < 2; b++)
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setbits_le32(&ch[chn].phy.b[b].dq[7],
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0x1 << 6 | 0x1 << 4 | 0x1 << 2 | 0x1 << 0);
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}
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setbits_le32(&ch[chn].phy.ca_cmd[7], 0x1 << 6 | 0x1 << 4 | 0x1 << 2 | 0x1 << 0);
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setbits_le32(&ch[chn].phy.ca_cmd[2], 0x1 << 21);
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@ -245,11 +243,11 @@ static void ddr_phy_pll_setting(u8 chn, u8 freq_group)
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setbits_le32(&ch[chn].phy.b[1].dll_fine_tune[3],
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(0x1 << 11) | (0x1 << 13) | (0x1 << 14) | (0x1 << 15) |
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(0x1 << 17));
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clrbits_le32(&ch[chn].phy.ca_dll_fine_tune[2],
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(0x1 << 10) | (0x1 << 13) |
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(0x1 << 15) | (0x1 << 16) | (0x1 << 17) |
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(0x1 << 19) | (0x1 << 27) | (0x1 << 31));
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clrbits_le32(&ch[chn].phy.b[0].dll_fine_tune[2],
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(0x1 << 10) | (0x1 << 13) | (0x1 << 14) |
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(0x1 << 15) | (0x1 << 17) |
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@ -323,7 +321,7 @@ static void dramc_gating_mode(u8 mode)
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static void update_initial_settings(u8 freq_group)
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{
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u8 chn = 0, operate_fsp = get_freq_fsq(freq_group);
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u8 operate_fsp = get_freq_fsq(freq_group);
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u16 rx_vref = 0x16;
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if (operate_fsp == FSP_1)
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@ -380,7 +378,7 @@ static void update_initial_settings(u8 freq_group)
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clrsetbits_le32(&ch[0].phy.b[b].dq[5], 0x3f << 8, rx_vref << 8);
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}
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for (chn = 0; chn < CHANNEL_MAX; chn++) {
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for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
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setbits_le32(&ch[chn].phy.b[0].dq[8], (0x1 << 0) | (0x1 << 1) | (0x1 << 2));
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setbits_le32(&ch[chn].phy.b[1].dq[8], (0x1 << 0) | (0x1 << 1) | (0x1 << 2));
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setbits_le32(&ch[chn].phy.ca_cmd[9], (0x1 << 0) | (0x1 << 1) | (0x1 << 2));
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@ -398,7 +396,7 @@ static void update_initial_settings(u8 freq_group)
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clrbits_le32(&ch[0].phy.shu[0].ca_cmd[5], 0x3f << 8);
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dramc_set_broadcast(DRAMC_BROADCAST_OFF);
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for (chn = 0; chn < CHANNEL_MAX; chn++) {
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for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
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clrbits_le32(&ch[chn].phy.shu[0].b[0].dq[6], 0x3f << 0);
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clrbits_le32(&ch[chn].phy.shu[0].b[1].dq[6], 0x3f << 0);
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clrbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], 0x3f << 0);
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@ -504,13 +502,8 @@ static void update_initial_settings(u8 freq_group)
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setbits_le32(&ch[0].ao.ckectrl, 0x1 << 22);
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clrsetbits_le32(&ch[0].phy.ca_tx_mck, (0x1 << 31) | (0x1f << 21) | (0x1f << 26),
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(0x1 << 31) | (0xa << 21) | (0xa << 26));
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setbits_le32(&ch[0].ao.ckectrl, 0x1 << 23);
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/* Gating error problem happened in M17
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* has been solved by setting this RG as 0 */
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clrbits_le32(&ch[0].ao.shu[0].rodtenstb, 0x1 << 31);
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}
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static void dramc_power_on_sequence(void)
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@ -548,7 +541,7 @@ static void ddr_phy_reserved_rg_setting(u8 freq_group)
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/* fine tune */
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for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
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clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], 0xFFFF << 6,
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clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], 0xffff << 6,
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(0x1 << 6) | ((!chn) << 7) | (hyst_sel << 8) |
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(midpi_cap_sel << 9) | (0x1 << 10) | (0x3 << 17) | (lp3_sel << 20));
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@ -678,9 +671,9 @@ static u8 dramc_zq_calibration(u8 chn, u8 rank)
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const u32 TIMEOUT_US = 100;
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struct reg_value regs_bak[] = {
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{&ch[chn].ao.mrs, 0x0},
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{&ch[chn].ao.dramc_pd_ctrl, 0x0},
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{&ch[chn].ao.ckectrl, 0x0},
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{&ch[chn].ao.mrs},
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{&ch[chn].ao.dramc_pd_ctrl},
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{&ch[chn].ao.ckectrl},
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};
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for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++)
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@ -732,8 +725,8 @@ static void dramc_mode_reg_init(u8 freq_group)
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u8 MR22Value[FSP_MAX] = {0x38, 0x34};
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MR01Value[FSP_0] &= 0x8F;
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MR01Value[FSP_1] &= 0x8F;
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MR01Value[FSP_0] &= 0x8f;
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MR01Value[FSP_1] &= 0x8f;
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if (freq_group == LP4X_DDR1600) {
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MR02Value[0] = 0x12;
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@ -754,7 +747,7 @@ static void dramc_mode_reg_init(u8 freq_group)
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MR01Value[FSP_0] |= (0x5 << 4);
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MR01Value[FSP_1] |= (0x5 << 4);
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} else if (freq_group == LP4X_DDR3600) {
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MR02Value[0] = 0x1A;
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MR02Value[0] = 0x1a;
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MR02Value[1] = 0x36;
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MR01Value[FSP_0] |= (0x6 << 4);
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@ -870,13 +863,9 @@ static void dramc_setting_DDR1600(void)
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(0x2 << 8) | (0x2 << 12) |
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(0x1 << 16) | (0x1 << 20) | (0x1 << 24) | (0x1 << 28));
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clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[2],
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0x77777777,
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(0x1 << 0) | (0x1 << 4) | (0x1 << 8) | (0x1 << 12) |
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(0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28));
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0x77777777, _SELPH_DQS_BITS(0x1, 0x7));
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clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[3],
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0x77777777,
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(0x1 << 0) | (0x1 << 4) | (0x1 << 8) | (0x1 << 12) |
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(0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28));
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0x77777777, _SELPH_DQS_BITS(0x1, 0x7));
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}
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clrsetbits_le32(&ch[0].ao.shu[0].dqsg_retry, (0x1 << 2) | (0xf << 8),
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@ -933,13 +922,9 @@ static void dramc_setting_DDR2400(void)
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(0x3 << 8) | (0x3 << 12) |
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(0x3 << 16) | (0x3 << 20) | (0x3 << 24) | (0x3 << 28));
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clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[2],
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0x77777777,
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(0x2 << 0) | (0x2 << 4) | (0x2 << 8) | (0x2 << 12) |
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(0x0 << 16) | (0x0 << 20) | (0x0 << 24) | (0x0 << 28));
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0x77777777, _SELPH_DQS_BITS(0x2, 0x0));
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clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[3],
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0x77777777,
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(0x2 << 0) | (0x2 << 4) | (0x2 << 8) | (0x2 << 12) |
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(0x0 << 16) | (0x0 << 20) | (0x0 << 24) | (0x0 << 28));
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0x77777777, _SELPH_DQS_BITS(0x2, 0x0));
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}
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clrsetbits_le32(&ch[0].ao.shu[0].dqsg_retry,
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@ -1109,26 +1094,25 @@ static void dramc_setting(const struct sdram_params *params, u8 freq_group)
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clrsetbits_le32(&ch[0].phy.shu[0].b[b].dq[6], 0xffff << 6, 0x1 << 6);
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dramc_set_broadcast(DRAMC_BROADCAST_OFF);
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for (size_t chan = 0; chan < 2; chan++)
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clrsetbits_le32(&ch[chan].phy.misc_shu_opt,
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for (chn = 0; chn < CHANNEL_MAX; chn++)
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clrsetbits_le32(&ch[chn].phy.misc_shu_opt,
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(0x1 << 0) | (0x3 << 2) | (0x1 << 8) |
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(0x3 << 10) | (0x1 << 16) | (0x3 << 18),
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(0x1 << 0) | (0x2 << 2) | (0x1 << 8) |
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(0x2 << 10) | (0x1 << 16) | ((0x1+chan) << 18));
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(0x2 << 10) | (0x1 << 16) | ((0x1 + chn) << 18));
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udelay(9);
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clrsetbits_le32(&ch[0].phy.shu[0].ca_dll[1], (0x1 << 0) | (0x1 << 2), 0x1 << 2);
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clrsetbits_le32(&ch[1].phy.shu[0].ca_dll[1], (0x1 << 0) | (0x1 << 2), 0x1 << 0);
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dramc_set_broadcast(DRAMC_BROADCAST_ON);
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for (size_t b = 0; b < 2; b++) {
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for (size_t b = 0; b < 2; b++)
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clrsetbits_le32(&ch[0].phy.shu[0].b[b].dll[1],
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(0x1 << 0) | (0x1 << 2), (0x1 << 0) | (0x0 << 2));
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}
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udelay(1);
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clrbits_le32(&ch[0].phy.pll2, 0x1 << 31);
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clrsetbits_le32(&ch[0].phy.misc_cg_ctrl0, 0xffffffff, 0xF);
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clrsetbits_le32(&ch[0].phy.misc_cg_ctrl0, 0xffffffff, 0xf);
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udelay(1);
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dramc_set_broadcast(DRAMC_BROADCAST_OFF);
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@ -1224,21 +1208,13 @@ static void dramc_setting(const struct sdram_params *params, u8 freq_group)
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for (size_t rank = 0; rank < 2; rank++) {
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clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[0],
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0x77777777,
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(0x3 << 0) | (0x3 << 4) | (0x3 << 8) | (0x3 << 12) |
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(0x3 << 16) | (0x3 << 20) | (0x3 << 24) | (0x3 << 28));
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0x77777777, _SELPH_DQS_BITS(0x3, 0x3));
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clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[1],
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0x77777777,
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(0x3 << 0) | (0x3 << 4) | (0x3 << 8) | (0x3 << 12) |
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(0x3 << 16) | (0x3 << 20) | (0x3 << 24) | (0x3 << 28));
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0x77777777, _SELPH_DQS_BITS(0x3, 0x3));
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clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[2],
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0x77777777,
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(0x6 << 0) | (0x6 << 4) | (0x6 << 8) | (0x6 << 12) |
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(0x2 << 16) | (0x2 << 20) | (0x2 << 24) | (0x2 << 28));
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0x77777777, _SELPH_DQS_BITS(0x6, 0x2));
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clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[3],
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0x77777777,
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(0x6 << 0) | (0x6 << 4) | (0x6 << 8) | (0x6 << 12) |
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(0x2 << 16) | (0x2 << 20) | (0x2 << 24) | (0x2 << 28));
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0x77777777, _SELPH_DQS_BITS(0x6, 0x2));
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}
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for (int b = 0; b < 2; b++) {
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@ -1348,7 +1324,7 @@ static void dramc_setting(const struct sdram_params *params, u8 freq_group)
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clrsetbits_le32(&ch[0].ao.shu[0].stbcal, 0x7 << 4, 0x1 << 4);
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if (freq_group == LP4X_DDR1600)
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clrsetbits_le32(&ch[0].ao.shu[0].stbcal, 0x3 << 0, (0x0 << 0));
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clrsetbits_le32(&ch[0].ao.shu[0].stbcal, 0x3 << 0, 0x0 << 0);
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else
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clrsetbits_le32(&ch[0].ao.shu[0].stbcal, 0x3 << 0, 0x2 << 0);
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setbits_le32(&ch[0].ao.refctrl1, (0x1 << 0) | (0x1 << 5));
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@ -73,7 +73,7 @@ void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term)
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clrsetbits_le32(&ch[0].phy.misc_imp_ctrl0, 0x7 << 4, 0x3 << 4);
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udelay(1);
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dramc_show("K DRVP\n");
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dramc_dbg("impedance: K DRVP\n");
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setbits_le32(&ch[0].ao.impcal, 0x1 << 23);
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setbits_le32(&ch[0].ao.impcal, 0x1 << 22);
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clrbits_le32(&ch[0].ao.impcal, 0x1 << 21);
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@ -88,18 +88,18 @@ void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term)
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udelay(1);
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imp_cal_result = (read32(&ch[0].phy_nao.misc_phy_rgs_cmd) >>
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24) & 0x1;
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dramc_show("1. OCD DRVP=%d CALOUT=%d\n",
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dramc_dbg("1. OCD DRVP=%d CALOUT=%d\n",
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impx_drv, imp_cal_result);
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if (imp_cal_result == 1 && DRVP_result == 0xff) {
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DRVP_result = impx_drv;
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dramc_show("1. OCD DRVP calibration OK! DRVP=%d\n",
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dramc_dbg("1. OCD DRVP calibration OK! DRVP=%d\n",
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DRVP_result);
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break;
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}
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}
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dramc_show("K ODTN\n");
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dramc_dbg("impedance: K ODTN\n");
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dramc_sw_imp_cal_vref_sel(term, IMPCAL_STAGE_DRVN);
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clrbits_le32(&ch[0].ao.impcal, 0x1 << 22);
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if (term == ODT_ON)
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@ -116,12 +116,12 @@ void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term)
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udelay(1);
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imp_cal_result = (read32(&ch[0].phy_nao.misc_phy_rgs_cmd) >>
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24) & 0x1;
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dramc_show("3. OCD ODTN=%d CALOUT=%d\n",
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dramc_dbg("3. OCD ODTN=%d CALOUT=%d\n",
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impx_drv, imp_cal_result);
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|
||||
if (imp_cal_result == 0 && ODTN_result == 0xff) {
|
||||
ODTN_result = impx_drv;
|
||||
dramc_show("3. OCD ODTN calibration OK! ODTN=%d\n",
|
||||
dramc_dbg("3. OCD ODTN calibration OK! ODTN=%d\n",
|
||||
ODTN_result);
|
||||
break;
|
||||
}
|
||||
|
|
@ -129,7 +129,7 @@ void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term)
|
|||
|
||||
write32(&ch[0].ao.impcal, impcal_bak);
|
||||
|
||||
dramc_show("term:%d, DRVP=%d, DRVN=%d, ODTN=%d\n",
|
||||
dramc_show("impedance: term=%d, DRVP=%d, DRVN=%d, ODTN=%d\n",
|
||||
term, DRVP_result, DRVN_result, ODTN_result);
|
||||
if (term == ODT_OFF) {
|
||||
impedance[term][0] = DRVP_result;
|
||||
|
|
|
|||
|
|
@ -204,7 +204,6 @@ static void move_dramc_tx_dq_oen(u8 chn, u8 rank,
|
|||
|
||||
static void write_leveling_move_dqs_instead_of_clk(u8 chn)
|
||||
{
|
||||
dramc_dbg("%s do ch:%d k\n", __func__, chn);
|
||||
for (u8 byte = 0; byte < DQS_NUMBER; byte++) {
|
||||
move_dramc_tx_dqs(chn, byte, -WRITE_LEVELING_MOVD_DQS);
|
||||
move_dramc_tx_dqs_oen(chn, byte, -WRITE_LEVELING_MOVD_DQS);
|
||||
|
|
@ -394,7 +393,7 @@ void dramc_apply_config_before_calibration(u8 freq_group)
|
|||
setbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 24);
|
||||
clrsetbits_le32(&ch[0].ao.shu[0].scintv, 0x1f << 1, 0x1b << 1);
|
||||
|
||||
for (size_t shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++)
|
||||
for (size_t shu = DRAM_DFS_SHUFFLE_1; shu < DRAM_DFS_SHUFFLE_MAX; shu++)
|
||||
setbits_le32(&ch[0].ao.shu[shu].conf[3], 0x1ff << 0);
|
||||
|
||||
clrbits_le32(&ch[0].ao.dramctrl, 0x1 << 18);
|
||||
|
|
@ -409,15 +408,14 @@ void dramc_apply_config_before_calibration(u8 freq_group)
|
|||
for (size_t chn = 0; chn < CHANNEL_MAX; chn++) {
|
||||
setbits_le32(&ch[chn].ao.spcmdctrl, 0x1 << 29);
|
||||
setbits_le32(&ch[chn].ao.dqsoscr, 0x1 << 24);
|
||||
for (size_t shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++)
|
||||
for (size_t shu = DRAM_DFS_SHUFFLE_1; shu < DRAM_DFS_SHUFFLE_MAX; shu++)
|
||||
setbits_le32(&ch[chn].ao.shu[shu].scintv, 0x1 << 30);
|
||||
|
||||
clrbits_le32(&ch[chn].ao.dummy_rd, (0x1 << 7) | (0x7 << 20));
|
||||
dramc_hw_gating_onoff(chn, false);
|
||||
clrbits_le32(&ch[chn].ao.stbcal2, 0x1 << 28);
|
||||
|
||||
setbits_le32(&ch[chn].phy.misc_ctrl1,
|
||||
(0x1 << 7) | (0x1 << 11));
|
||||
setbits_le32(&ch[chn].phy.misc_ctrl1, (0x1 << 7) | (0x1 << 11));
|
||||
clrbits_le32(&ch[chn].ao.refctrl0, 0x1 << 18);
|
||||
clrbits_le32(&ch[chn].ao.mrs, 0x3 << 24);
|
||||
setbits_le32(&ch[chn].ao.mpc_option, 0x1 << 17);
|
||||
|
|
@ -966,13 +964,13 @@ static void dramc_rx_dqs_gating_cal(u8 chn, u8 rank, u8 freq_group,
|
|||
u32 coarse_start, coarse_end;
|
||||
|
||||
struct reg_value regs_bak[] = {
|
||||
{&ch[chn].ao.stbcal, 0x0},
|
||||
{&ch[chn].ao.stbcal1, 0x0},
|
||||
{&ch[chn].ao.ddrconf0, 0x0},
|
||||
{&ch[chn].ao.spcmd, 0x0},
|
||||
{&ch[chn].ao.refctrl0, 0x0},
|
||||
{&ch[chn].phy.b[0].dq[6], 0x0},
|
||||
{&ch[chn].phy.b[1].dq[6], 0x0},
|
||||
{&ch[chn].ao.stbcal},
|
||||
{&ch[chn].ao.stbcal1},
|
||||
{&ch[chn].ao.ddrconf0},
|
||||
{&ch[chn].ao.spcmd},
|
||||
{&ch[chn].ao.refctrl0},
|
||||
{&ch[chn].phy.b[0].dq[6]},
|
||||
{&ch[chn].phy.b[1].dq[6]},
|
||||
};
|
||||
for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++)
|
||||
regs_bak[i].value = read32(regs_bak[i].addr);
|
||||
|
|
@ -2136,7 +2134,8 @@ int dramc_calibrate_all_channels(const struct sdram_params *pams, u8 freq_group)
|
|||
u8 rx_datlat[RANK_MAX] = {0};
|
||||
for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
|
||||
for (u8 rk = RANK_0; rk < RANK_MAX; rk++) {
|
||||
dramc_show("Start K ch:%d, rank:%d\n", chn, rk);
|
||||
dramc_show("Start K: freq=%d, ch=%d, rank=%d\n",
|
||||
freq_group, chn, rk);
|
||||
dramc_auto_refresh_switch(chn, false);
|
||||
dramc_cmd_bus_training(chn, rk, freq_group, pams,
|
||||
fast_calib);
|
||||
|
|
|
|||
|
|
@ -43,7 +43,7 @@ static int mt_mem_test(void)
|
|||
(i == 0) ? "pass" : "fail", i);
|
||||
|
||||
if (i != 0) {
|
||||
dramc_show("DRAM memory test failed\n");
|
||||
printk(BIOS_ERR, "DRAM memory test failed\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
|
@ -80,7 +80,7 @@ static int dram_run_fast_calibration(const struct dramc_param *dparam,
|
|||
return -1;
|
||||
}
|
||||
|
||||
if (dparam->header.config != config) {
|
||||
if (dparam->header.config != config) {
|
||||
printk(BIOS_WARNING,
|
||||
"Incompatible config for calibration data from flash "
|
||||
"(expected: %#x, saved: %#x)\n",
|
||||
|
|
@ -167,7 +167,7 @@ void mt_mem_init(struct dramc_param_ops *dparam_ops)
|
|||
set_source_to_flash(dparam->freq_params);
|
||||
dparam_ops->write_to_flash(dparam);
|
||||
printk(BIOS_DEBUG, "Calibration params saved to flash: "
|
||||
"version=%#x, size=#%x\n",
|
||||
"version=%#x, size=%#x\n",
|
||||
dparam->header.version, dparam->header.size);
|
||||
return;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue