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northbridge/amd/amdmct/mct_ddr3: Update prefetcher configuration 

The existing prefetcher configuration was incorrect; use the correct
values from the AMD Family 10h and Family 15h BKDGs as appropriate.

Change-Id: I287ffa6345e1f4d232d4b2ea4251650ada3fda92
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12417
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Timothy Pearson 2015-11-11 19:01:41 -06:00 committed by Stefan Reinauer
parent 7fd3ef57cb
commit 31ec0f3257
1 changed files with 5 additions and 2 deletions
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7
src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
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@ -2408,9 +2408,12 @@ static void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat,
} while (!(val & (1 << Dr_MemClrStatus)));
}
val = 0x0FE40FC0; /* BKDG recommended */
if (is_fam15h())
val = 0x0ce00f41; /* BKDG recommended */
else
val = 0x0fe40fc0; /* BKDG recommended */
val |= MCCH_FlushWrOnStpGnt; /* Set for S3 */
Set_NB32(dev, 0x11C, val);
Set_NB32(dev, 0x11c, val);
}
static u8 NodePresent_D(u8 Node)